Pulsed-Bias Comparator Circuit for Fast Low-Power Response
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Solution Overview
Problem
Integrated circuit comparators face challenges in reducing propagation delay while maintaining or reducing power consumption, as existing methods often result in increased power consumption with faster propagation speeds.
Innovation Solution
Implementing a pulsed bias current in the input gain stage of the comparator, with a voltage limiter and built-in hysteresis circuit to optimize ngain node voltage excursion and minimize capacitive loading, allowing the comparator to quickly respond to voltage changes with reduced quiescent current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If continuous bias current is applied to the input gain stage, then the comparator responds quickly to voltage changes, but the quiescent power consumption increases
Solution Approach 1:
The patent applies periodic pulsed bias current to the input gain stage instead of continuous DC bias. The bias current is activated only during the comparison window controlled by clock signals (phi1 and phi2), allowing the comparator to respond quickly during active periods while consuming minimal power during idle periods. This periodic activation resolves the contradiction between fast response and low quiescent power consumption.
2Loss of time
If the voltage excursion of the ngain node is reduced to a minimum, then the propagation delay is reduced, but the capacitive loading effects become more significant
Solution Approach 1:
The voltage limiter circuit is pre-configured to clamp the ngain node voltage excursion before it can reach levels that would cause significant capacitive loading effects. By limiting the voltage swing in advance, the circuit achieves fast propagation delay while preventing the harmful capacitive loading effects from occurring during the comparison operation.
Data Source
AI summary
A direct relationship exists between an integrated comparator's propagation delay and the input differential pair's bias current and overdrive voltage. A new method using a pulsed bias scheme for the input differential pair improves propagation delay by more than one order of magnitude without increasing significantly the average quiescent current, as long as the pulse width of the bias current is small relative to the system clock. A voltage limiter optimizes the comparator's transition time and a built-in hysteresis circuit minimizes spurious output transitions whenever the pulsed bias current pulse changes state. The bias current pulse and sampling of the comparator occur in predefined relation to the system clock.