Pulsed-Bias Plasma Etching for FinFET Sidewall Damage Control
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Solution Overview
Problem
In the semiconductor industry, particularly during the manufacturing of FinFETs, there is a challenge in achieving defect-free and damage-free fin structures due to ion bombardment during plasma etching, which affects the precision and performance of the devices.
Innovation Solution
A novel process involving pulsed-bias voltage plasma etching and subsequent annealing operations is employed to reduce and eliminate damage on the fin structures, using specific conditions such as DC and RF power settings, gas mixtures, and annealing temperatures to maintain ion-neutral species balance and re-crystallize damaged areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma etching is used to form fin structures, then manufacturing precision is improved, but sidewall damage increases
Solution Approach 1:
The patent applies pulsed bias voltage during plasma etching, alternating between high bias voltage (ion bombardment phase) and low or zero bias voltage (neutral species deposition phase). This periodic action allows ions to etch the fin structure while neutral species simultaneously passivate the sidewalls, preventing damage accumulation and achieving precise fin formation without sidewall degradation
Solution Approach 2:
The patent dynamically changes plasma process parameters during etching, specifically modulating bias voltage between different levels in pulses, adjusting gas flow rates, and controlling pressure variations. These parameter changes enable control over the balance between ion bombardment (for etching precision) and neutral species flux (for sidewall protection), resolving the contradiction between manufacturing precision and sidewall damage
2Productivity
If continuous high bias voltage is applied during plasma etching, then etching speed increases, but fin structure damage increases
Solution Approach 1:
The patent employs pulsed bias voltage with alternating high and low voltage phases. During high voltage phases, ion bombardment provides rapid etching speed. During low voltage phases, reduced ion damage allows neutral species to heal and passivate the surface. This periodic modulation maintains high average etching speed while preventing cumulative damage to the fin structure
Solution Approach 2:
The patent ensures continuous useful action by maintaining plasma presence throughout the pulsed cycle, with neutral species continuously available during low bias phases to protect the fin structure. This continuous protective action, combined with periodic high-speed etching phases, maintains productivity while preventing damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses sidewall damage, maintains fin structure integrity, and enhances device performance by reducing defects and surface roughness, leading to improved yield and reduced leak current.
Implementation Method 1
pulsed-bias voltage plasma etching
Implementation Method 2
ion bombardment during plasma etching
Implementation Method 3
annealing operation is performed on the fin structure
Implementation Method 4
re-crystallize damaged areas
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.