Pulsed Bias for Flash Memory Data Retention and Power
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Solution Overview
Problem
Flash storage devices experience charge loss in cells due to electron migration, leading to bit errors and reduced data retention, and constant biasing to improve data retention results in inefficient power consumption, especially in power-off devices.
Innovation Solution
The implementation of pulsed biasing during power-up and read recovery, where the controller applies voltage pulses with specific amplitudes and widths based on the number of program/erase cycles, to maintain data retention while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If constant biasing is applied to improve data retention, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent applies pulsed biasing instead of constant biasing, where voltage pulses are applied periodically or selectively to word lines during specific operations (power-up, read recovery) rather than continuously. This periodic action maintains data retention benefits while significantly reducing overall power consumption in flash storage devices.
Solution Approach 2:
The patent applies voltage pulses during power-up before normal operations begin, and during read recovery when errors are detected. This preliminary action prevents charge loss before it occurs (power-up) or corrects it when detected (read recovery), eliminating the need for continuous biasing and thereby reducing power consumption while maintaining reliability.
2Reliability
If voltage pulses are applied to reduce charge loss, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameters of voltage application by using pulsed biasing with specific pulse widths and amplitudes that are functions of the number of program/erase cycles. This parameter change allows the system to adapt to cell degradation over time while maintaining simple control logic through standardized pulse generation.
Solution Approach 2:
The system automatically applies pulsed biasing during power-up and read recovery operations based on predefined conditions, eliminating the need for complex external control mechanisms. The controller independently manages the timing and parameters of voltage pulses based on operational state and P/E cycle count.
Data Source
AI summary
A storage device is provided that applies pulsed biasing during power-up or read recovery. The storage device includes a memory and a controller. The memory includes a block having a word line and cells coupled to the word line. The controller applies a voltage pulse to the word line during power-up or in response to a read error. The voltage pulse may include an amplitude and a pulse width that are each a function of a number of P/E cycles of the block. The controller may also perform pulsed biasing during both power-up and read recovery by applying one or more first voltage pulses to the word line during power-up and one or more second voltage pulses to the word line in response to a read error. As a result, lower bit error rates due to wider Vt margins may occur and system power may be saved over constant biasing.