Pulsed-Clock Data Latch for Low-Glitch Flip-Flops
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Solution Overview
Problem
Conventional semiconductor integrated circuit devices face significant power consumption challenges due to high glitch power in flip-flops, which is exacerbated by the difficulty in equalizing delay times among flip-flops, making it impractical to prevent glitches in synchronous circuits.
Innovation Solution
The implementation of a pulse-generator-incorporated auto-clock-gating flip-flop design, where a pulsed clock with a 50% duty ratio is used to separate data incorporation and retention periods, minimizing feedback control and reducing power consumption by preventing glitches through precise clock control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional clock gating is implemented in flip-flops, then power consumption is reduced, but glitch power increases due to unequal delay times among flip-flops
Solution Approach 1:
The patent applies periodic action by using a pulsed clock signal with a 50% duty cycle that periodically enables and disables the flip-flop. The clock signal is gated to provide pulses only during specific periods when data changes occur, rather than continuously clocking the flip-flop. This periodic gating reduces power consumption while the pulse width and timing are controlled to avoid glitch conditions that would otherwise occur with conventional clock gating approaches.
2Object-generated harmful factors
If delay times among flip-flops are equalized to prevent glitches, then glitch power is reduced, but device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent implements self-service by designing the flip-flop with automatic clock gating functionality that detects and responds to data change conditions internally. The flip-flop structure includes logic that automatically generates clock enable signals based on the data input and current state, eliminating the need for external delay equalization circuits or complex control logic. This self-service approach reduces glitch power without requiring additional complexity for delay matching.
3Ease of manufacture
If conventional flip-flop design is used, then design flow is simple, but power consumption is high due to continuous clocking
Solution Approach 1:
The patent achieves universality by designing a flip-flop structure that combines multiple functions into a single integrated cell: data latching, automatic clock gating, and glitch prevention all occur within the same flip-flop structure. This multi-functional design allows the circuit to operate with reduced power consumption while maintaining compatibility with standard design flows and existing flip-flop integration methodologies, making it universally applicable without requiring separate control circuits.
Data Source
AI summary
A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.