Pulsed Current Plating for PCB Via Holes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current plating technologies for printed circuit boards (PCBs) face challenges in achieving high-speed signal transmission and sufficient heat dissipation due to differences in thermal expansion coefficients between materials, leading to reliability issues and inadequate heat dissipation characteristics, especially when trying to enhance heat dissipation through staggered or stacked vias.
Innovation Solution
A method involving pulsed current electroplating is applied to PCBs, where opposite polarity pulses and overlapping forward current periods are used to separate plating accelerators and suppressors within the through holes, concentrating the plating accelerator at the center to ensure uniform plating from the middle to the end of the holes, forming a first plating layer with fine and coarse grain regions, and a second layer filling recessed grooves on the surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If plating is performed only on the wall surface of the hole, then the plating process is simple, but the heat dissipation characteristic is insufficient and reliability is low due to CTE differences
Solution Approach 1:
The patent changes the plating parameters by applying pulsed current instead of continuous current, and by controlling the plating to fill the hole completely rather than stopping at the wall surface. This results in the plating material filling the entire via hole, eliminating the interface between copper plating and insulating resin, thereby resolving the CTE difference issue and improving reliability.
2Ease of manufacture
If plating is performed only on the wall surface of the hole, then the manufacturing process is simple, but the heat dissipation characteristic is insufficient
Solution Approach 1:
The patent modifies the plating process parameters to achieve complete hole filling, transforming the via structure from a wall-surface-only plating to a full-hole filling plating. This ensures that the via hole is completely filled with conductive plating material, creating effective thermal pathways for heat dissipation while maintaining manufacturing feasibility through controlled pulsed current electroplating.
3Temperature
If stacked vias are used to enhance heat dissipation, then heat dissipation characteristics improve, but cracks and delamination occur and signal noises are generated
Solution Approach 1:
The patent applies pulsed current electroplating with controlled parameters to fill via holes completely, creating a uniform conductive structure throughout the hole. This complete filling approach eliminates the need for staggered or stacked via configurations that cause mechanical stress and signal interference, thereby preventing cracks, delamination, and signal noises while maintaining effective heat dissipation.
4Ease of manufacture
If plating accelerator and suppressor are not separated, then the plating process is simple, but uniform plating cannot be achieved
Solution Approach 1:
The patent employs pulsed current electroplating with periodic application and cessation of current. During the pulsed on-period, metal ions are deposited on the cathode; during the pulsed off-period, the plating accelerator and suppressor molecules have time to separate and redistribute. This periodic action enables uniform plating throughout the via hole while maintaining process simplicity, as the same pulsed current source controls both deposition and molecular separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances both high-speed signal transmission and heat dissipation capabilities by ensuring uniform plating and reducing the thickness of the plating layers, thereby improving the reliability and performance of PCBs.
Implementation Method 1
applying a pulsed current to each surface of the substrate, comprising applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole
Data Source
AI summary
A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.