Pulsed Flip-Flop Level Shifting Across Multiple Voltage Domains
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Solution Overview
Problem
Conventional level shifter circuits in integrated circuits face challenges in efficiently transmitting signals across multiple voltage domains, particularly when synchronously transmitting signals, leading to high area consumption and contention between voltage domains.
Innovation Solution
A pulsed flip-flop design is implemented, comprising a master circuit and a slave circuit with pre-charge input and resolving circuits, capable of level shifting and operating across multiple voltage domains, allowing for efficient signal transmission without requiring supply voltages from both domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional level shifter circuits are used to transmit signals across voltage domains, then signal transmission between voltage domains is enabled, but area consumption increases and contention between voltage domains occurs
Solution Approach 1:
The patent combines the level shifting function with the flip-flop circuit into a single integrated structure. The master flip-flop circuit operates at a first voltage domain while the slave flip-flop circuit operates at a second voltage domain, merging the voltage domain transition function with the data latching function to eliminate the need for separate level shifter circuits.
Solution Approach 2:
The flip-flop circuit performs multiple functions simultaneously: it latches data signals across clock cycles and transitions signals between different voltage domains. This multi-functional design eliminates the need for dedicated level shifter circuits, reducing overall area consumption while maintaining signal transmission capability across voltage domains.
2Ease of operation
If conventional level shifter circuits are used for synchronous signal transmission, then clock signal synchronization is enabled, but additional supply voltage requirements increase device complexity
Solution Approach 1:
The patent divides the flip-flop circuit into master and slave segments operating at different voltage domains. The master flip-flop circuit is supplied by a first voltage domain while the slave flip-flop circuit is supplied by a second voltage domain, allowing each segment to operate independently at its appropriate voltage level without requiring additional supply voltages.
Solution Approach 2:
The patent uses voltage domain segmentation as an intermediary mechanism to enable synchronous signal transmission. By having the master and slave flip-flop circuits operate at different voltage domains with appropriate voltage supply separation, the circuit achieves clock signal synchronization without requiring additional supply voltages that would increase device complexity.
3Adaptability or versatility
If conventional level shifter circuits are used for signal transmission, then voltage domain transition is enabled, but latency and delay in signal propagation increase
Solution Approach 1:
The patent merges the voltage domain transition function with the data latching function in a single integrated flip-flop circuit. This eliminates the need for separate level shifter stages that would add propagation delay, as the voltage domain transition occurs simultaneously with the data latching operation within the same circuit structure.
Data Source
AI summary
Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.