Pulsed Latch Clocking for Lower-Power Flip-Flop Replacement
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Solution Overview
Problem
Integrated circuits consume significant dynamic power due to the use of edge-triggered flip-flops, which can be reduced by replacing them with pulsed latches, but existing techniques lack efficient methods for designing circuit modifications that maintain performance and power reduction.
Innovation Solution
A circuit design system and methodology that automatically replaces edge-triggered flip-flops with pulsed latches, using pulse generators and delay cells to maintain timing and power efficiency, while optimizing skew, slew, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If edge-triggered flip-flops are used to propagate data synchronously with a periodic clock signal, then data propagation reliability is improved, but dynamic power consumption increases
Solution Approach 1:
The patent applies periodic action by using pulsed latches that are triggered by periodic pulse signals instead of continuous periodic clock signals. The pulse generators create narrow periodic pulses that activate the latches only during specific intervals, reducing the time during which power is consumed while maintaining synchronous data propagation reliability.
Solution Approach 2:
The patent changes the clocking parameter from continuous periodic signals to narrow periodic pulses. By transforming the clock signal into short-duration pulses with controlled width and timing, the system maintains the necessary triggering functionality while significantly reducing the duration of high-power states, thereby lowering dynamic power consumption.
2Manufacturing precision
If a clock tree network is used to route clock signals to flip-flops, then timing synchronization is improved, but dynamic power consumption increases
Solution Approach 1:
The patent replaces the continuous periodic clock distribution network with periodic pulse generation at multiple locations. Pulse generators distributed throughout the circuit create localized periodic pulses that trigger pulsed latches, eliminating the need for a high-power global clock tree while maintaining timing synchronization through controlled pulse propagation.
Solution Approach 2:
The patent segments the monolithic clock tree network into multiple independent pulse generators distributed throughout the circuit. Each pulse generator independently creates pulses for its local region, dividing the power-consuming clock distribution function into smaller segments that consume less total power while maintaining synchronization.
3Ease of operation
If the clock signal is periodically switched over high capacitance in the clock wiring network, then clock signal distribution is improved, but dynamic power consumption increases
Solution Approach 1:
The patent uses periodic narrow pulses instead of continuous periodic switching to drive the clock network. The pulse generators create brief periodic activations that trigger the latches without requiring sustained high-current switching, dramatically reducing the energy consumed during each clock cycle while maintaining effective signal distribution.
Solution Approach 2:
The patent employs short-duration pulses as the clocking mechanism, using brief bursts of energy instead of sustained switching. These short-lived pulse signals perform the necessary triggering function and then dissipate, avoiding the continuous energy expenditure required by traditional clock trees that must maintain signal levels throughout the entire clock period.
Data Source
AI summary
A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.