Pulsed Latch Timing Replica Circuit for Minimum Delay Errors
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Solution Overview
Problem
Minimum delay errors in digital integrated circuits, particularly in pulsed latch designs, pose severe challenges due to their potential to cause entire system failures and are difficult to correct without significant power consumption or re-spinning of the chip, leading to high costs and delayed time-to-market.
Innovation Solution
Implementing a minimum delay path replica circuit with error detection and tunable clock buffers, allowing for prediction and correction of minimum delay errors by adjusting the clock supply voltage and pulse width, thereby avoiding failures and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If pulsed latches are used instead of single-edged triggered flip flops, then clocking power consumption is reduced, but minimum delay errors become more severe and difficult to correct
Solution Approach 1:
The patent creates a replica of the minimum delay path with identical logic elements and routing to detect timing errors. The replica circuit copies the critical path characteristics to enable error detection without affecting the main data path operation, allowing detection of minimum delay errors that occur in pulsed latch designs.
Solution Approach 2:
The patent introduces an intermediary error detection circuit that monitors the output of the minimum delay path. This intermediary system captures error information and provides it to control logic, which then triggers correction actions. The intermediary acts as a bridge between the data path and control mechanisms.
2Reliability
If minimum delay errors are corrected by increasing voltage or re-spinning the chip, then error reliability is improved, but power consumption increases or manufacturing costs and time-to-market increase
Solution Approach 1:
The patent performs preliminary error detection by continuously monitoring the minimum delay path during normal operation. By detecting errors early before they propagate through the system, the patent enables immediate correction actions without requiring system shutdown, voltage changes, or chip re-spinning, thus maintaining time-to-market schedules.
Solution Approach 2:
The patent implements a feedback mechanism where the error detection circuit continuously monitors the data path and provides real-time error information to control logic. When an error is detected, the feedback triggers automatic correction actions such as adjusting clock timing or re-latching data, creating a closed-loop system that maintains reliability without external intervention.
3Manufacturing precision
If minimum delay errors are corrected by re-spinning the chip, then manufacturing precision is improved, but manufacturing costs increase and time-to-market is delayed
Solution Approach 1:
The patent introduces dynamic adjustment capabilities to the clocking system, allowing timing parameters to be modified after manufacturing. The control logic can dynamically adjust clock pulse width, timing skew, or latch enable signals to correct minimum delay errors without requiring physical manufacturing changes, making the system adaptable to process variations.
Solution Approach 2:
The patent changes operational parameters such as clock pulse width, clock timing skew, or latch control signals to correct minimum delay errors. By adjusting these parameters dynamically or through post-fabrication tuning, the patent achieves timing precision without requiring costly manufacturing re-spinning or physical modifications to the chip.
Data Source
AI summary
A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.