Pulsed Latch Circuit With Dynamic Pulse Width Shutoff
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Solution Overview
Problem
In high-performance integrated circuits, the narrow clock pulses used in pulsed latch circuits make them susceptible to process variations, leading to issues with hold time and setup time trade-offs, which can result in either degraded performance or circuit failure.
Innovation Solution
A pulsed latch circuit with conditional shutoff is introduced, utilizing a condition generator and variable delay circuit to adjust the input signal width and detect proper data latching, allowing the latch to shut off once data is captured, thereby reducing the impact of process variations and optimizing setup and hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock pulse width is narrowed to increase operating speed, then the speed of operation is improved, but the circuit becomes more susceptible to process variations and may collapse with no clock signal to registers
Solution Approach 1:
The latch circuit dynamically adjusts its operation mode between transparent and locked states based on the clock signal phase. The transmission gate is controlled to be transparent during the high phase of the clock signal, allowing data to pass through, and locked during the low phase, holding the data stable. This dynamic switching enables the circuit to operate reliably with narrow clock pulses while maintaining data integrity.
2Reliability
If the pulse width is widened to ensure proper latching, then reliability is improved, but the hold time increases causing functional failure and slowing down circuit performance
Solution Approach 1:
The latch circuit operates in periodic cycles synchronized with the clock signal. During the high phase of the clock signal, the transmission gate is transparent and data is latched. During the low phase, the latch enters a locked state where the data is held stable. This periodic operation allows the circuit to achieve reliable latching with short pulse widths while minimizing hold time, as the latch only needs to maintain data during the brief low phase rather than for an extended period.
3Productivity
If a narrow pulse is used to meet speed requirements, then productivity is improved, but the susceptibility to process variations increases affecting circuit stability
Solution Approach 1:
The latch circuit incorporates feedback through the cross-coupled NOR gates that form the latch core. The output of each NOR gate is fed back to the input of the other, creating a stable feedback loop that maintains the latched state. This feedback mechanism ensures that once data is latched during the high clock phase, it remains stable during the low phase even with narrow pulses, compensating for process variations and maintaining circuit stability at high speeds.
Data Source
AI summary
A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.