Pulsed Latch Clocking for Two-Cycle FIFO Storage
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Solution Overview
Problem
Traditional flip-flop circuits can only store one value per clock cycle, limiting their storage efficiency and requiring additional circuits to achieve higher storage capacities.
Innovation Solution
The implementation of pulsed latch circuits with a clock control circuit that generates first and second clock pulses, allowing the latches to store values from two successive clock cycles, effectively converting a flip-flop into a two-stage FIFO circuit by selectively modifying the clocking mechanism without affecting the data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional flip-flop circuits are used, then the circuit structure is simple, but the storage capacity is limited to one value per clock cycle
Solution Approach 1:
The patent applies dynamics by making the clock signal dynamic through pulse generation. Instead of using a static clock signal that triggers both latches simultaneously, the invention generates dynamic clock pulses with different widths for each latch. The first latch receives a full clock cycle pulse while the second latch receives a shortened pulse, creating temporal differentiation that enables the latches to operate at different phases within the same clock cycle, thereby doubling storage capacity without adding external circuits
Solution Approach 2:
The patent implements periodic action through the clock control circuit that generates periodic clock pulses for the latches. The clock control circuit divides the incoming clock signal into periodic pulses with specific width relationships, where the first latch is triggered by pulses of one width and the second latch by pulses of another width. This periodic pulsing mechanism allows the latches to sequentially capture data values from different clock cycles, achieving increased storage capacity through time-multiplexed periodic operation
2Quantity of substance
If additional circuits are added to increase storage capacity, then the storage efficiency improves, but the area overhead increases
Solution Approach 1:
The patent applies universality by making the existing latch circuits multi-functional. Instead of adding separate storage circuits for each additional value, the invention enables the existing two latches to serve multiple storage purposes by triggering them at different times within the same clock cycle. The same physical latch structures are used to store different values from different clock cycles, eliminating the need for additional storage circuits and reducing area overhead while doubling effective storage capacity
Solution Approach 2:
The patent transitions from spatial dimensionality to temporal dimensionality. Rather than adding more latches in parallel (spatial expansion), the invention exploits the time dimension by generating clock pulses of different widths that cause latches to trigger at different moments within the same clock cycle. This temporal differentiation allows the same physical circuit area to store multiple values sequentially, effectively adding a time dimension to the storage operation and doubling capacity without increasing area
3Quantity of substance
If the clock signal is modified to trigger latches at different times, then the storage capacity doubles, but the clock control complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the clock control circuit with fixed pulse width relationships. The clock control circuit is designed in advance to generate specific pulse widths for each latch based on the incoming clock signal, eliminating the need for real-time dynamic adjustment during operation. The pulse generation logic is established beforehand, allowing the latches to automatically trigger at the correct times without complex runtime control, thus achieving doubled storage capacity with manageable control complexity
Data Source
AI summary
The disclosed pulsed latched circuitry includes first and second latch circuits. The first and second latch circuits can be provided with additional logic circuit components to permit them to be operated as a flip-flop circuit, or as a FIFO circuit with a depth of two.