Pulsed Latch Level Shifter for High-Voltage, High-Frequency Operation
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Solution Overview
Problem
Existing ultrasound system transmitters face challenges with level shifters due to non-immunity to high supply transients, large area requirements due to high voltage transistors, and inability to support high operating frequencies, which affect the reliability and efficiency of ultrasound imaging systems.
Innovation Solution
A level shifter design that uses low voltage transistors, minimizing static power losses and dynamic power losses, and incorporates capacitors to shield nodes from voltage supply transients, allowing for higher frequency operation and reduced area usage while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used in the level shifter, then the high voltage domain can be achieved, but the area occupied increases significantly
Solution Approach 1:
The patent introduces a latch circuit as an intermediary mechanism between the low voltage domain and high voltage domain. The latch stores the voltage level information and enables level shifting without requiring large-area high voltage transistors in the critical signal path, thus reducing the overall area while maintaining high voltage capability
Solution Approach 2:
The level shifter is divided into multiple functional blocks: a first logic block for generating control signals, a latch for storing voltage level information, and a second logic block for generating the final output. This segmentation allows each block to be optimized independently, reducing the total area required while achieving the high voltage level shifting function
2Reliability
If existing level shifters are used in high voltage applications, then they can perform basic level shifting, but they are not immune to high supply transients
Solution Approach 1:
The latch circuit is designed to store the voltage level information before transient disturbances occur. By maintaining the stored state during supply transients, the circuit prevents transient propagation to the output, effectively cushioning against the harmful effects of supply variations
Solution Approach 2:
The latch circuit provides feedback mechanisms that monitor the voltage levels and adjust the output accordingly during transient events. This feedback ensures that the level shifter maintains its functionality and immunity to supply transients by continuously correcting any transient-induced deviations
3Reliability
If high voltage transistors are used in the level shifter, then the high voltage domain can be achieved, but the operating frequency is limited
Solution Approach 1:
The latch acts as an intermediary that decouples the high voltage switching operations from the high-frequency signal path. By storing voltage level information in the latch rather than using high voltage transistors for direct switching, the circuit achieves both high voltage capability and high-frequency operation
Solution Approach 2:
The level shifter uses periodic clock signals to control the latch and logic blocks, enabling synchronized operation at high frequencies. The periodic clocking mechanism allows the circuit to maintain high voltage capability while operating at frequencies determined by the clock signal, rather than being limited by transistor switching speeds
4Reliability
If conventional level shifters are used, then they can perform level shifting, but they incur static power losses
Solution Approach 1:
The level shifter uses periodic clock signals to activate the latch and logic blocks only when needed, rather than maintaining continuous operation. This periodic activation eliminates static power losses by ensuring that power-consuming components are inactive during idle periods, while still maintaining the level shifting function when required
Data Source
AI summary
The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.