Pulsed-Latch Layout Using Continuous OD Regions for LOD Matching
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Solution Overview
Problem
Integrated circuits face performance variations due to differing physical characteristics between transistors, particularly at reduced sizes, leading to challenges in designing layouts with high numbers of transistors within a small area, affecting drive current and timing precision.
Innovation Solution
Bridging oxide-on-diffusion (OD) regions to form continuous regions, incorporating dummy transistors that act as decoupling capacitors to reduce physical stress and performance mismatches, thereby enhancing transistor similarity and circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are reduced in size to increase density, then the number of transistors per area increases, but performance variations between transistors worsen due to physical characteristic differences
Solution Approach 1:
The patent applies local quality by creating a non-uniform oxide layer thickness across the diffusion region. The oxide layer is thinner at the edges and thicker toward the center, compensating for the mechanical stress that edge transistors experience from shallow trench isolation. This localized variation in oxide thickness adjusts the electrical characteristics of transistors at different positions, ensuring more uniform performance across the entire array despite size reduction.
2Ease of manufacture
If oxide-on-diffusion regions are separated to accommodate layout constraints, then manufacturing flexibility improves, but transistor performance mismatch worsens due to length-of-diffusion effects
Solution Approach 1:
The patent merges multiple separate oxide-on-diffusion regions into a continuous, unified diffusion region. This consolidation eliminates the length-of-diffusion effects that occur at the boundaries of separate regions, where transistors experience different mechanical stress and electrical characteristics. By creating a single continuous region with a gradient oxide layer, the patent ensures that all transistors operate under more uniform conditions, improving matching while still allowing layout flexibility through the gradient structure.
3Area of stationary object
If edge transistors are retained in the design, then device area utilization improves, but performance mismatch with center transistors worsens due to mechanical stress from isolation edges
Solution Approach 1:
The patent applies local quality by creating a non-uniform oxide layer thickness across the diffusion region. The oxide layer is thinner at the edges and thicker toward the center, compensating for the mechanical stress that edge transistors experience from shallow trench isolation. This localized variation in oxide thickness adjusts the electrical characteristics of transistors at different positions, ensuring more uniform performance across the entire array despite size reduction.
Data Source
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AI summary
A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.