Pulsed-Latch Phase Frequency Detector for Shorter Reset Delay
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Solution Overview
Problem
Conventional phase frequency detectors have a large reset loop delay due to the use of D flip-flops, limiting their maximum operating frequency and increasing power consumption.
Innovation Solution
A fast phase frequency detector is designed using fast pulsed-latches with clock and reset control, replacing D flip-flops to shorten the reset loop delay and improve circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If D flip-flops are used in the phase frequency detector, then the circuit structure is relatively simple, but the reset loop delay becomes large which limits the maximum operating frequency
Solution Approach 1:
The patent changes the fundamental parameter of the flip-flop architecture from conventional D flip-flop to pulsed-latch structure. This parameter change fundamentally alters the reset loop delay characteristics, enabling the maximum operating frequency to exceed 10GHz while reducing the reset loop delay to approximately 100ps. The pulsed-latch structure achieves this by using clocked transmission gates that are controlled by non-overlapping clock phases, creating a fundamentally different timing behavior compared to edge-triggered D flip-flops.
2Use of energy by moving object
If D flip-flops are used in the phase frequency detector, then the implementation is straightforward, but the power consumption increases
Solution Approach 1:
The patent implements periodic action by using non-overlapping clock phases (PHI1 and PHI2) to control the transmission gates in the pulsed-latch structure. The clock signal is divided into two non-overlapping phases that periodically enable and disable the transmission gates, creating a pulsed operation mode. This periodic control allows the circuit to remain in a low-power state during idle periods while maintaining functionality during active phases, thereby reducing overall power consumption compared to continuously operating D flip-flops.
Data Source
AI summary
A fast phase frequency includes two fast pulsed-latches, a NAND gate, and an adjustable delay circuit, where the fast pulsed-latches include a pulse generating circuit, a reset circuit, and an output latch circuit. The pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level. The output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid, and the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.