Multi-bit Pulsed Latch Serial Scan Chain Power Optimization
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Solution Overview
Problem
Conventional sequential cells in electronic devices often fail to meet power consumption specifications, despite using common clock signals to control data transfer among multiple flip-flops or latches, leading to inefficiencies in power management.
Innovation Solution
The implementation of improved latches with an internal chain and pulse generators that generate separate timing signals, allowing the chain to be deactivated during normal operation to reduce power consumption, and activated during test modes for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple sequential cells use a common clock signal to control data transfer, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent divides the single common clock signal into multiple separate timing signals (first timing signal and second timing signal) that are distributed to different stages of the sequential cells. This segmentation allows independent control of clock distribution to each stage, enabling selective activation and deactivation of timing signal distribution to reduce power consumption while maintaining functional complexity management.
Solution Approach 2:
The patent implements dynamic control by using a control signal to selectively enable or disable the distribution of the second timing signal to the second stage of sequential cells during different operational modes (test mode vs. normal operation mode). This dynamic adjustment allows the system to optimize power consumption based on operational requirements without permanently increasing device complexity.
2Measurement precision
If the scan chain is activated for test mode operation, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic switching between operational modes by using a control signal that selectively enables the scan chain functionality during test mode while disabling it during normal operation mode. This allows the system to achieve precise test measurement capabilities when needed while minimizing power consumption during normal operation by deactivating the scan chain timing signal distribution.
Solution Approach 2:
The patent enables periodic activation of the scan chain functionality, where the second timing signal is distributed to the second stage only during periodic test operations rather than continuously. This periodic action allows measurement precision to be improved during test modes while power consumption is reduced during normal operation modes when the scan chain is deactivated.
Data Source
AI summary
Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.