Pulsed Latch State Retention With Dual Power Domains
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing system on chip (SoC) designs face challenges in reducing both power consumption and area without increasing design complexity, particularly in standard cell designs, while maintaining state retention during power-down modes.
Innovation Solution
A pulsed latch system utilizing two power supplies, a continuous supply (VDDC) for state retention and a switchable supply (VDD) for the rest of the system, powered down during low power modes, along with a shared pulse generator in multi-bit configurations to reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional latch design is used to maintain state retention, then state is preserved during power-down modes, but leakage power consumption increases
Solution Approach 1:
The latch circuit is divided into two separate power domains: a first power domain (VDDC) that remains active during power-down modes to maintain state retention, and a second power domain (VDD) that can be powered down to reduce leakage power. This segmentation allows different parts of the circuit to be powered independently based on their functional requirements.
Solution Approach 2:
Different power supply voltages are applied to different portions of the latch circuit. The state retention portion receives continuous power from VDDC while the combinational logic portion receives power from the switchable VDD supply. This local quality differentiation enables selective power management to reduce overall leakage while preserving state.
2Loss of energy
If power is reduced by powering down components, then leakage power decreases, but state may be lost from the latch
Solution Approach 1:
The power supply system is segmented into a continuous supply (VDDC) dedicated to state retention and a switchable supply (VDD) for combinational logic. By keeping VDDC active while powering down VDD, the latch maintains its state without requiring the combinational logic to remain powered.
Solution Approach 2:
The first power supply (VDDC) acts as an intermediary that bridges the gap between needing to power down for low power modes and needing to retain state. It provides minimal continuous power specifically to the latch portion that requires state retention, decoupling state maintenance from full system power requirements.
3Loss of energy
If standard cell designs are used for low power techniques, then area and power can be reduced, but design complexity increases
Solution Approach 1:
The pulsed latch cell is designed as a universal building block that can be used in various low power modes and configurations. It incorporates multiple power supply interfaces and control mechanisms that allow it to function in different power management scenarios, reducing the need for specialized cells for each mode.
Solution Approach 2:
The latch design utilizes controllable parameters such as pulse width and power supply voltages to optimize performance for different operating conditions. By adjusting these parameters, the same cell design can achieve low power consumption in standby modes while maintaining full functionality in active modes, without requiring multiple specialized designs.
Data Source
AI summary
An integrated circuit includes a pulse generator having at least one delay circuit with an input that receives a clock signal and an output that provides a delayed clock pulse. The delayed clock pulse has a width proportional to an amount of time required to maintain a magnitude of the clock signal. A pulse latch circuit includes a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.