Pulsed Wide-Range Level Shifter for Low-Delay Voltage Translation
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Solution Overview
Problem
Conventional level shifters in integrated circuits face challenges such as large delay times, leakage issues, and reliability degradation due to wide variability in voltage domains, leading to malfunction and reduced retention time in eDRAMs, especially when charge pump output varies with PVT fluctuations.
Innovation Solution
The implementation of a pulsed level shifter with a pulse generator and droop circuit, and a self-collapsing level shifter with an embedded drooping mechanism, which generates a pulse to decouple the level shifter from the voltage supply during transitions, reducing contention and leakage, and utilizing power gating to minimize power consumption and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifters are used to interface components operating at different voltage supplies, then voltage level translation is achieved, but large delay times and leakage currents occur
Solution Approach 1:
The level shifter uses dynamic control signals (phi1, phi2) to actively manage transistor switching states during voltage level translation. The control logic dynamically adjusts the timing and sequence of transistor activation to minimize delay while preventing leakage paths, resolving the contradiction between reliable signal translation and fast operation.
Solution Approach 2:
The level shifter employs periodic clocking signals (phi1, phi2) to control the translation process in discrete phases. This periodic action allows the circuit to systematically manage the transition between voltage levels, ensuring reliable signal transfer while minimizing overlap that would cause leakage and reducing overall delay time.
2Adaptability or versatility
If conventional level shifters operate across wide voltage domains, then voltage translation is achieved, but leakage currents increase and retention time decreases
Solution Approach 1:
The level shifter prepares the output transistors in advance by pre-charging or pre-discharging nodes before the actual signal transition. This preliminary action ensures that when the signal switches between wide voltage domains, leakage paths are minimized and retention time is maintained, as the circuit is already in the optimal state for the upcoming transition.
Solution Approach 2:
The level shifter incorporates feedback mechanisms that monitor the output voltage level and adjust the control signals accordingly. This feedback ensures that when operating across wide voltage domains, the circuit maintains proper transistor switching states that prevent leakage currents while preserving signal integrity and retention time.
3Power
If charge pump output varies with PVT fluctuations, then voltage supply is provided, but level shifter malfunction and retention time degradation occur
Solution Approach 1:
The level shifter uses dynamic control logic that adapts to variations in charge pump output caused by PVT fluctuations. The control signals (phi1, phi2) are dynamically adjusted based on the actual voltage levels present, ensuring reliable operation across process, voltage, and temperature variations while maintaining proper retention time.
Solution Approach 2:
The level shifter modifies its operating parameters (transistor switching timing, control signal levels) in response to changes in charge pump output voltage. This parameter adaptation allows the circuit to maintain reliable operation and retention time even when the voltage supply varies due to PVT fluctuations.
4Adaptability or versatility
If more level shifters are added to handle voltage domain variations, then signal translation coverage is improved, but power consumption and area overhead increase
Solution Approach 1:
The level shifter is designed as a universal circuit that can handle multiple voltage domain translations using the same basic architecture. By making the level shifter multi-functional and adaptable to different voltage scenarios, the design reduces the total number of specialized level shifters needed, thereby lowering overall power consumption and area overhead while maintaining wide voltage domain coverage.
Data Source
AI summary
Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.