Pulsed Level Shifter Circuitry for Time Borrowing Across Voltage Domains
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Solution Overview
Problem
Traditional circuitry does not allow time borrowing across voltage domains, limiting the ability of level-shifting circuitry to relax edge-to-edge timing requirements and facilitate efficient data transfer between circuits operating at different voltage levels.
Innovation Solution
The implementation of level-shifting circuitry that generates a pulse signal based on an input clock edge, allowing the input to change during the pulse and enabling time borrowing by transparently passing and level shifting the input, with pull and feedback circuits driving and maintaining the output across voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional level-shifting circuitry is used, then voltage level conversion is achieved, but time borrowing across voltage domains is not allowed
Solution Approach 1:
The patent employs periodic clock signals to control the level-shifting circuitry, enabling synchronized operation across voltage domains. The clocked architecture allows for periodic sampling and transfer of signals, which creates well-defined timing windows that support time borrowing while maintaining reliability through regular clocked operation.
Solution Approach 2:
The patent introduces intermediate latches and buffer stages between different voltage domains. These intermediary elements act as temporary storage points that decouple the timing requirements of source and destination circuits, enabling time borrowing by holding signals until the receiving domain is ready without compromising signal integrity.
2Length of moving object
If edge-to-edge timing requirements are enforced, then timing precision is maintained, but combinational path length is limited
Solution Approach 1:
The patent uses preliminary latching actions before signals cross voltage domains. By capturing signals in latches prior to level shifting, the circuit establishes a known good state early in the timing sequence, which allows longer combinational paths to follow without accumulating timing errors, effectively extending the allowable path length.
Solution Approach 2:
The patent implements feedback mechanisms that monitor signal propagation through the combinational logic. This feedback allows the system to dynamically adjust timing margins and compensate for variations in path length, enabling longer combinational paths while maintaining effective timing precision through adaptive correction.
3Ease of operation
If time borrowing is enabled across voltage domains, then timing flexibility is improved, but circuit complexity increases
Solution Approach 1:
The patent divides the level-shifting circuitry into modular segments, each handling a specific voltage domain transition. This segmentation allows time borrowing to be implemented in a distributed manner across multiple simple stages rather than requiring one complex circuit, reducing overall complexity while maintaining timing flexibility.
Solution Approach 2:
The patent designs universal level-shifting cells that can operate in multiple modes (normal operation, time borrowing, different voltage transitions). These multi-functional blocks reduce the need for separate dedicated circuits for each function, achieving timing flexibility without proportionally increasing complexity through component reuse and standardized interfaces.
Data Source
AI summary
Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.