Pulsed Mode Analog Block Power Reduction via Top-Up Buffer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face significant power consumption challenges due to always-active core analogue blocks, which are inefficient, especially in battery-operated devices, as they consume power even in low power modes, affecting battery life and performance.
Innovation Solution
Implementing a Pulsed Mode operation with a Top-Up Buffer amplifier and fast Bypass Comparator to reduce the ON-time of core analogue blocks, dynamic control of commutating components, and charge holding capacitors to minimize power consumption while maintaining voltage levels, allowing for shorter ON times and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If core analogue blocks are kept always active to ensure functionality, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements pulsed mode operation where core analogue blocks are activated periodically rather than continuously. The control logic activates these blocks only when needed (e.g., during mode transitions or when voltage references need updating) and keeps them inactive during steady-state operation, thereby dramatically reducing power consumption while maintaining functionality.
2Use of energy by moving object
If ultra-low current designs are used to reduce power consumption, then energy efficiency is improved, but circuit performance deteriorates
Solution Approach 1:
The patent employs dynamic control of commutating components to optimize the balance between power consumption and performance. By dynamically switching between different operational modes and adjusting activation timing based on actual circuit needs, the system achieves low average power consumption while maintaining adequate performance levels during active periods.
3Use of energy by moving object
If ON-time of analog blocks is reduced to save power, then power efficiency is improved, but voltage reference accuracy may deteriorate
Solution Approach 1:
The patent uses charge holding capacitors to pre-charge and store voltage reference values before entering low-power mode. This preliminary action ensures that when the analog blocks are reactivated, the voltage references are already established and accurate, eliminating the need for prolonged activation times while maintaining precision.
4Use of energy by moving object
If dynamic control of commutating components is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The control logic is designed to autonomously manage the activation and deactivation of core analogue blocks based on predefined conditions and internal state monitoring. This self-service approach minimizes the need for external control signals and complex timing mechanisms, reducing overall device complexity while achieving effective power management.
Data Source
Figure 1A~1B
Figure 2
Figure 3~5
AI summary
Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks - internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation. A Dynamic Control of the Commutating Components ensures least disturbance of the voltage potentials, thus allowing shorter ON times and respectively better power efficiency. The invention can also be applied to reference voltage and to bias current generator circuits.