Pulsed Scan Flip-Flop Circuit for Lower Setup Time and Leakage
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Solution Overview
Problem
Conventional flip-flops in integrated circuits face challenges in achieving low power consumption, high performance, and efficient scan chain operations, particularly in mobile applications, due to high setup times, negative hold times, and increased leakage power.
Innovation Solution
A device comprising a pulse generator circuit with a NOR gate and a pulse-controlled latch circuit, along with a mode selection circuit using a multiplexer, which generates a pulse signal based on a clock signal and controls latching operations, optimizing flip-flop design by reducing transistor count and improving timing balances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flip-flop designs are used, then basic data storage function is achieved, but setup times are high and performance is limited
Solution Approach 1:
The flip-flop is segmented into distinct functional blocks: pulse generator circuit, mode selection circuit, and latch circuit. This segmentation allows each block to be optimized independently, with the pulse generator specifically designed to produce precise clock pulses that reduce setup time requirements while maintaining overall circuit performance.
Solution Approach 2:
The pulse generator circuit generates clock pulses in advance of the main clock signal edge, preparing the latch circuit for data capture. This preliminary action reduces the effective setup time by pre-enabling the latch to receive data before the actual clock transition occurs.
2Loss of energy
If conventional flip-flop designs are used, then data storage is achieved, but leakage power is increased
Solution Approach 1:
The latch circuit operates in periodic cycles, being enabled only during the brief pulse window generated by the pulse generator. During inactive periods, the latch remains disabled, minimizing leakage current while maintaining data retention through the inherent stability of the latch structure during active periods.
Solution Approach 2:
The flip-flop transitions from a static conventional design to a dynamic pulsed architecture where the latch enable signal varies over time. This dynamic operation allows the circuit to achieve low leakage power by disabling the latch during intervals when data capture is not required, while maintaining reliability through precise timing control.
3Loss of time
If conventional flip-flop designs are used, then basic operation is achieved, but hold and setup rise/fall times are unbalanced
Solution Approach 1:
The pulse generator circuit provides locally optimized timing characteristics by generating asymmetric pulses with specifically controlled rise and fall times. This local quality adjustment allows the hold time and setup time to be independently optimized, creating a balanced timing profile that improves overall ease of operation without compromising basic flip-flop functionality.
4Adaptability or versatility
If scan chain operations are added, then testing capability is improved, but device complexity increases
Solution Approach 1:
The mode selection circuit implements universality by allowing the flip-flop to operate in multiple modes: normal data storage mode and scan chain mode. The same basic flip-flop structure serves dual purposes, reducing overall device complexity compared to having separate circuits for each function. The multiplexer and mode control signal enable a single circuit to perform both data storage and scan operations.
Data Source
AI summary
A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.