Pulsed Serial Link With Edge-Timed Data and Return Acknowledgment
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Solution Overview
Problem
Synchronous integrated circuit designs face challenges with clock signal distribution, leading to cross-talk and transistor degradation, while asynchronous designs are complex and prone to metastability issues, requiring additional resources for flow control.
Innovation Solution
A method and apparatus for transmitting clock and data on a single line using a pulsed serial link, where a first edge represents a timing edge and a second edge represents data, with a selectable time period for the data edge, and a return pulse for acknowledgement, allowing for efficient communication between modules without the need for separate clock and data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous design with clock signal distribution is used, then timing control is simplified and modules can operate reliably, but cross-talk and power consumption increase due to high drive strength requirements
Solution Approach 1:
The patent extracts the clock signal from the data transmission line by using edge timing of data pulses to represent clock transitions. The receiving module detects rising and falling edges of data pulses to recover timing information without requiring a separate clock distribution network, thereby eliminating clock-related cross-talk and power consumption while maintaining synchronous timing control reliability
Solution Approach 2:
The patent combines clock and data transmission into a single data line by encoding timing information within the data pulse edges. The clock signal is embedded in the transitions of data pulses, allowing both clock and data to be transmitted over the same physical medium, reducing the number of tracks and associated harmful effects
2Object-generated harmful factors
If asynchronous design without clock signal is used, then cross-talk and power consumption are reduced, but design complexity and metastability risks increase significantly
Solution Approach 1:
The patent implements a handshake protocol with acknowledgment signals where the receiving module sends feedback to the transmitting module to confirm data reception. This feedback mechanism ensures reliable asynchronous communication by coordinating transmission and reception events, preventing metastability without requiring complex synchronous timing infrastructure
Solution Approach 2:
The patent uses preliminary signaling where the receiving module prepares acknowledgment signals in advance and the transmitting module waits for confirmation before sending subsequent data. This preliminary coordination simplifies asynchronous design by establishing a predictable interaction pattern that avoids metastability without complex timing analysis
3Reliability
If additional feedback paths are added for asynchronous flow control, then reliable communication is achieved, but resource requirements and logic complexity increase
Solution Approach 1:
The patent combines the feedback acknowledgment signal with the data transmission line by using the same physical medium for both directions of communication. The single bidirectional link carries both data from transmitter to receiver and acknowledgments from receiver to transmitter, reducing resource requirements while maintaining reliable flow control
Solution Approach 2:
The patent makes the single communication link universal by enabling it to carry multiple functions: data transmission in one direction and acknowledgment feedback in the opposite direction. This multi-functional use of the same physical resource achieves reliable asynchronous communication without requiring separate dedicated feedback paths
Data Source
AI summary
Apparatus for transmitting a clock and data from a first module to a second module connected by a single outward line and a single return line, comprising: means for transmitting a data pulse on the single outward line comprising means for asserting a first edge on said single outward line, said first edge representing a timing edge for the clock and means for asserting a second edge on the single outward line a selectable time period after said first edge, said selectable time period representing said data; and means for receiving a return pulse on said single return path comprising means for receiving a first edge and a second edge on the single return line, the first and second edges being separated by a first time period, said first time period representing an acknowledgement.