Printable Pulsed Voltage Multiplier Circuit Topology
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Solution Overview
Problem
Traditional voltage multipliers in printed electronics face challenges due to low thin film transistor (TFT) ON/OFF ratios and currents, limited diode current, and capacitor leakage, necessitating alternative circuit designs that reduce component complexity and production costs while enabling high voltage delivery for limited durations.
Innovation Solution
A pulsed voltage multiplier architecture comprising multiple stages with trigger voltage terminals, input and output terminals, and capacitors, where each stage is connected to a supply voltage, allowing for controlled output pulse width and amplitude through a printing process using organic Schottky diodes, polymer capacitors, and carbon resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional voltage pumps are used in printed electronics, then voltage multiplication is achieved, but device complexity and production costs increase due to low TFT ON/OFF ratios, limited diode current, and capacitor leakage
Solution Approach 1:
The voltage multiplier is divided into multiple identical stages, each consisting of a transistor, diode, and capacitor. This segmentation allows the complex voltage multiplication function to be achieved through repetition of simple, standardized units, reducing overall design complexity while maintaining reliability.
Solution Approach 2:
The invention changes the operating parameters by using pulsed voltage multiplication instead of continuous operation. Each stage operates in discrete cycles with controlled timing, allowing the circuit to overcome limitations of low TFT ON/OFF ratios and capacitor leakage by resetting and recharging in controlled intervals.
2Ease of manufacture
If traditional additive printing processes are used to manufacture devices, then device fabrication is achieved, but production speed decreases and costs increase
Solution Approach 1:
The patent uses a universal printing process that can fabricate multiple different components (transistors, diodes, capacitors, interconnects) using the same ink formulations and printing techniques. This multi-functionality eliminates the need for separate manufacturing processes for each component type, significantly increasing production speed while maintaining ease of manufacture.
Solution Approach 2:
The invention changes the material parameters by developing ink formulations with widely separated printabilities, allowing all components to be printed using the same process conditions. This parameter optimization enables high-speed production without sacrificing manufacturing ease.
3Adaptability or versatility
If multiple types of components are used in voltage multipliers, then functional requirements are met, but production costs and complexity increase due to multiple ink formulations and print heads
Solution Approach 1:
The patent achieves universality by designing a voltage multiplier circuit where all components (transistors, diodes, capacitors, interconnects) are fabricated using the same printing process and ink formulations. This universal approach maintains full circuit functionality while eliminating the need for multiple specialized components, processes, and equipment.
Solution Approach 2:
The invention merges the fabrication of different component types into a single integrated printing process. Instead of separately manufacturing transistors, diodes, and capacitors with different techniques, all components are printed together in the same process, reducing complexity in both device structure and manufacturing system.
Data Source
AI summary
A voltage multiplier includes a supply voltage, at least two multiplier stages electrically connected together, each stage having a trigger voltage terminal, an input terminal, an output terminal, and a capacitor, and each stage connected to the supply voltage, an input stage electrically connected to a first of the at least two multiplier stages, and an output stage electrically connected to a final of the at least two multiplier stages.