Monolithic Punch-Through Interconnect for Multi-Level DRAM Capacitors
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Solution Overview
Problem
Existing interconnect features for capacitors in semiconductor memory devices, such as DRAMs, are complex and complicate the processing of memory/logic layers, necessitating a simplified and efficient method for forming interconnects that access capacitor electrodes.
Innovation Solution
The formation of a continuous and monolithic interconnect feature, which is formed subsequent to memory cell and logic circuit formation, allowing access to capacitor electrodes through a single conductive via with a high aspect ratio, simplifying the patterning process and reducing the number of masks required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional interconnect features are used to access capacitor electrodes in multi-level memory arrays, then the memory device can be manufactured with existing processes, but the processing complexity increases and the number of masks required increases
Solution Approach 1:
The patent combines multiple interconnect functions into a single continuous monolithic conductive structure that punches through multiple conductive layers (first and second conductive structures) to access capacitor electrodes. This merging eliminates the need for separate interconnect features for each layer, reducing processing complexity and the number of masks required while maintaining manufacturing feasibility
2Productivity
If multiple separate interconnect features are formed to access capacitor electrodes in different layers, then each layer can be accessed independently, but the number of deposition processes and masks increases
Solution Approach 1:
The continuous monolithic interconnect structure is formed with preliminary punching action through all required conductive layers (first and second conductive structures) in a single deposition process. This preliminary formation of the complete interconnect path eliminates the need for subsequent separate deposition steps and mask alignments, significantly improving productivity and reducing processing time
Data Source
AI summary
An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.