Punch-Through Memory Cell Impact Ionization Read Stability
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Solution Overview
Problem
Current semiconductor memory cells, particularly DRAM cells with electrically floating bodies, face challenges in efficiently writing and reading data states due to sensitivity to technology variations and charge retention issues, leading to potential data loss during multiple read operations.
Innovation Solution
The implementation of a punch-through mode transistor with a body region having a different conductivity type, where the transistor operates by generating punch-through currents to represent data states, allowing for efficient writing and reading of data states through impact ionization and bipolar transistor currents, with circuitry to manage control signals for optimal retention and non-disturbing read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM cells with electrically floating bodies are used, then data storage is achieved, but charge retention deteriorates during multiple read operations
Solution Approach 1:
The patent changes the operational parameters of the transistor by inducing punch-through mode through specific voltage applications to source and drain regions. This parameter change enables impact ionization that generates and stores charge in the floating body, improving data retention characteristics while allowing non-destructive reads
2Ease of operation
If conventional read operations are performed on floating body memory cells, then data is read, but charge degradation occurs
Solution Approach 1:
The patent applies preliminary voltage pulses to the source and drain regions before the actual read operation to induce punch-through and generate charge through impact ionization. This preliminary action ensures sufficient charge is present in the floating body to enable reading without degrading previously stored data
Solution Approach 2:
The patent employs feedback mechanisms where the read operation itself generates charge through punch-through current that flows through the floating body. This feedback ensures that the act of reading replenishes the charge rather than depleting it, preventing charge degradation
3Adaptability or versatility
If floating body transistors are used for memory storage, then data states can be represented, but sensitivity to technology variations increases
Solution Approach 1:
The patent utilizes the self-service property where the transistor's own floating body structure generates and maintains the charge through punch-through induced impact ionization. This self-service mechanism reduces dependence on precise external control parameters and manufacturing tolerances, as the system self-regulates the charge storage through the punch-through phenomenon
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention characteristics and reduces charge degradation during multiple read operations, providing a more stable read window and improved sensitivity to technology variations, thus improving the overall performance of semiconductor memory cells.
Implementation Method 1
writing or programming a logic state one (1) includes applying control signals to the transistor to induce impact ionization to generate charge in the floating body
Implementation Method 2
the transistor, in operation, operates in a punch-through
Implementation Method 3
reading the data state includes applying control signals to the transistor to generate a bipolar transistor current that is representative of the data state
Data Source
AI summary
An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.