Pure Silicon Oxide Interfacial Layer on SiGe Channel
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Solution Overview
Problem
The scaling of traditional silicon dioxide gate dielectric layers in CMOS technologies leads to increased leakage current, while high-k gate dielectrics face interface issues with SiGe channels due to poor passivation and high interface trap charges, degrading device performance.
Innovation Solution
A method is developed to form a pure silicon oxide interfacial layer on a SiGe channel using a specific oxynitridation process, devoid of germanium oxide and nitrogen, which is used in conjunction with a high-k dielectric layer to reduce interface trap charges and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If SiO2 gate dielectric layer thickness is decreased to maintain capacitance, then device scaling is enabled, but leakage current increases exponentially
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of a high-k dielectric layer (such as HfO2, Ta2O5, or TiO2) combined with a thin interfacial silicon oxide layer. This composite structure enables thicker effective gate dielectric while maintaining the required capacitance, thereby reducing leakage current. The high-k material provides the necessary capacitance with greater thickness, and the interfacial SiO2 layer ensures proper interface with the SiGe channel.
2Object-generated harmful factors
If high-k gate dielectric materials are used to reduce leakage, then gate dielectric thickness can be increased, but interface trap density increases due to poor passivation with SiGe
Solution Approach 1:
The patent introduces a thin interfacial silicon oxide layer as an intermediary between the high-k dielectric material and the SiGe channel. This interfacial layer serves as a mediator that provides excellent interface passivation, reducing interface trap density and improving the electrical characteristics of the device. The interfacial SiO2 layer creates a high-quality interface while allowing the high-k material to maintain its leakage-reducing benefits.
3Object-generated harmful factors
If nitridation of silicon oxide layer is performed to suppress GeOx formation, then GeOx formation is reduced, but interface trap charge density increases and mobility degrades
Solution Approach 1:
The patent extracts and removes the problematic nitrogen element from the gate dielectric structure by avoiding nitridation processes. Instead of using nitrogen-containing dielectric layers, the invention employs a pure silicon oxide interfacial layer combined with a high-k dielectric layer that does not require nitrogen for GeOx suppression. This extraction of nitrogen eliminates the source of interface trap charge that would otherwise degrade carrier mobility.
4Reliability
If a thin interfacial silicon oxide layer is used with high-k dielectric, then interface quality improves, but optimization becomes non-trivial due to coexistence of Si and Ge interfacial oxides
Solution Approach 1:
The patent applies local quality by creating a distinct interfacial silicon oxide layer with specific properties at the SiGe channel interface, separate from the bulk high-k dielectric material. This localized SiO2 layer provides the necessary interface passivation quality, while the bulk high-k material provides the capacitance. The clear differentiation of functions and materials at different locations simplifies the overall process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses GeOx formation, reduces interface trap densities, and improves the mobility and subthreshold slope of SiGe-channel FET devices, achieving enhanced performance with a composite gate dielectric stack.
Implementation Method 1
growing a first silicon oxide layer on a first surface region of a SiGe layer using a first oxynitridation process
Implementation Method 2
growing a first silicon oxide layer on a first surface region of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen
Data Source
AI summary
Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.