PUSCH Interleaving Control for Shorter LTE TTI Processing
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Solution Overview
Problem
Current radio communication systems, particularly in LTE, lack a concrete method for reducing processing time within the Transmission Time Interval (TTI), which is essential for enhancing latency and efficiency.
Innovation Solution
The proposed solution involves optimizing the terminal and base station apparatuses to efficiently communicate by modifying the TTI processing through channel interleaving and transmission timing adjustments, allowing for reduced processing times in both uplink and downlink transmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional TTI processing is used, then system compatibility is maintained, but processing time is excessive and latency is high
Solution Approach 1:
The patent segments the TTI processing into distinct phases: a first processing period for receiving control signals and determining transmission parameters, and a second processing period for actual data transmission. This segmentation allows the terminal to perform critical operations in parallel during the first period, reducing overall processing time without excessive complexity increase.
Solution Approach 2:
The patent applies preliminary action by performing control signal reception, channel condition assessment, and transmission parameter determination during the first processing period before the actual data transmission begins. This advance preparation enables the second period to focus solely on efficient data transmission, reducing total latency.
2Loss of time
If processing time is reduced, then latency decreases, but processing accuracy may deteriorate
Solution Approach 1:
The patent implements self-service by enabling the terminal to autonomously determine transmission parameters such as modulation scheme, coding rate, and resource allocation based on channel conditions assessed during the first processing period. This self-determination maintains processing accuracy by using locally optimized parameters while reducing overall processing time through parallel operations.
Solution Approach 2:
The patent incorporates feedback mechanisms where the terminal continuously monitors channel conditions during the first processing period and adjusts transmission parameters accordingly. This feedback loop ensures processing accuracy is maintained even with reduced time by adapting to current channel states before transmission begins.
3Productivity
If uplink and downlink TTI lengths are kept equal, then design simplicity is maintained, but processing efficiency is suboptimal
Solution Approach 1:
The patent applies dynamics by allowing the first and second TTI lengths to be independently configurable based on service requirements. The system can dynamically adjust the duration of the first processing period and the second transmission period separately, enabling optimized processing efficiency for different traffic types without requiring complete redesign of the TTI structure.
Solution Approach 2:
The patent utilizes parameter changes by independently varying the time duration parameters of the first and second TTIs. This allows the system to optimize processing efficiency by adjusting the first TTI length for control operations and the second TTI length for data transmission separately, maintaining manageable design complexity through parameterization rather than structural redesign.
Data Source
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AI summary
A terminal apparatus includes: a receiver configured to detect a DCI format in a search space; a coding unit configured to divide a transport block into one or multiple code blocks, based at least on the DCI format and code the one or multiple code blocks to generate coded bits; and a transmitter configured to transmit the coded bits on a PUSCH. Multiplexed bits are given based at least on concatenation of the coded bits generated by coding the one or multiple code blocks. The coding unit maps the multiplexed bits to a matrix in a first-axis prioritized manner and reads out the multiplexed bits mapped to the matrix in the first-axis prioritized manner or a second-axis prioritized manner. Whether to prioritize the first axis or the second axis in a case of reading out the multiplexed bits mapped to the matrix, is based at least on whether or not the search space is CSS.