PUSCH Symbol Rate Processing With Split Buffers and Dual Streams
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Solution Overview
Problem
Conventional PUSCH receiver designs in 5G NR require significant FPGA resources due to buffering requirements, leading to high RAM consumption and complexity, with methods like DDR buffering being costly and resource-intensive, and BRAM congestion failing to meet timing requirements.
Innovation Solution
The PUSCH receiver is divided into a symbol rate processing (SRP) stage and a bit rate processing (BRP) stage, using a symbol separator buffer to store one slot of received data and an equalizer buffer to store one slot of equalized output, processing data with cyclic redundancy check decoding, and utilizing two separate streams for even and odd samples to complete SRP processing quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DDR buffering is used to store two slots of frequency grid data, then the PUSCH receiver can decode all scheduled UEs' data, but the design complexity and resource utilization increase significantly
Solution Approach 1:
The patent segments the buffering function into two separate BRAMs (first and second block random access memories) instead of using a single large DDR buffer. Each BRAM stores one slot of frequency grid data, allowing the system to process and decode data in manageable segments without requiring a single large memory block, thereby reducing controller complexity.
Solution Approach 2:
The patent uses volatile BRAM memory that can be quickly overwritten and refreshed, replacing the need for persistent DDR memory. The BRAMs are cleared and reused in each processing cycle, eliminating the need for complex DDR controllers while maintaining the ability to store and process two slots of data through sequential reading and overwriting.
2Ease of operation
If BRAMs are used to store one slot of frequency grid data, then memory access is simplified, but FPGA resource utilization increases significantly
Solution Approach 1:
The patent merges the functionality of multiple memory blocks into just two BRAMs that serve multiple purposes: storing frequency grid data for one slot, storing processed data for the next slot, and enabling ping-pong buffering. This consolidation reduces the total number of memory resources needed compared to using separate BRAMs for each function.
Solution Approach 2:
The two BRAMs are designed to perform multiple functions: they store frequency grid data, store processed frequency domain data, enable dual-slot processing, and support ping-pong buffering operations. This multi-functionality eliminates the need for dedicated separate memory blocks for each operation, reducing overall FPGA resource utilization while maintaining ease of access.
3Quantity of substance
If 320 BRAMs each of size 36 Kb are used to store two slots of data, then sufficient storage capacity is achieved, but BRAM congestion occurs and timing requirements are not met
Solution Approach 1:
The patent segments the storage of two slots of data into two separate BRAMs, where each BRAM handles one slot at a time. This segmentation allows parallel processing of different slots without requiring all 320 BRAMs to be simultaneously active, thereby reducing BRAM congestion and improving processing timing by allowing earlier slots to be processed while later slots are being stored.
4Reliability
If a buffer stores two slots of frequency grid data, then no data is overwritten before decoding, but the buffer consumes a lot of RAM in FPGA
Solution Approach 1:
The patent implements periodic action by using a ping-pong buffering scheme with two BRAMs that alternate between writing and reading operations. While one BRAM is being written with new slot data, the other BRAM is being read and processed. This periodic alternation ensures that data is not overwritten before decoding while maintaining constant buffer usage at only two BRAMs, rather than accumulating storage requirements for all pending data.
Data Source
AI summary
The present disclosure provides a system and a method for physical uplink shared channel (PUSCH) symbol rate processing. The system receives one or more signals from various users via a physical uplink shared channel (PUSCH). Further, the system bifurcates the input into two halves namely a symbol rate processing (SRP) stage and a bit rate processing (BRP) stage. The SRP stage stores one or more orthogonal frequency division multiplexing (OFDM) symbols associated with the signals. Further, the SRP stage processes the signal using an equalizer and stores an equalized output in an equalizer buffer. The equalizer uses two separate streams for processing even and odd samples and helps in completing the SRP stage quickly by reducing the processing time by fifty percent. The BRP stage receives an output from the equalizer buffer and decodes the output based on a user requirement.