Push-Pull Dynamic Amplifier Circuit for Stable High Gain
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Solution Overview
Problem
Prior art dynamic amplifiers require precise timing to achieve desired gain, with limited maximum gain due to early transition into the triode region, leading to noise dominance and reduced signal-to-noise ratio.
Innovation Solution
A push-pull dynamic amplifier circuit with NMOS and PMOS transistors, where the sizes of the transistors are configured to maintain equal drain currents during both reset and amplification phases, allowing for a more stable and extended period of optimal gain without critical timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a prior art dynamic amplifier uses a single type of input transistor (NMOS or PMOS), then the circuit complexity is reduced, but the maximum gain is limited and the amplifier enters the triode region early
Solution Approach 1:
The input stage is segmented into two complementary transistor types (NMOS and PMOS) operating in parallel. Each transistor type contributes differently to the overall transconductance, allowing the amplifier to achieve higher gain before entering the triode region. This segmentation enables independent optimization of each transistor's contribution to the total gain.
Solution Approach 2:
The invention changes the key parameter of transistor type from a single type to complementary types (NMOS and PMOS). By utilizing the different electrical characteristics of these transistor types, the amplifier achieves higher effective transconductance and extended linear operation range, thereby improving gain precision without excessive complexity.
2Manufacturing precision
If the amplifier operates for an extended period to achieve higher gain, then the gain increases, but the timing precision requirements become critical and noise increases
Solution Approach 1:
The complementary push-pull configuration enables continuous high-gain operation by maintaining balanced current flow through both NMOS and PMOS transistors. This continuity allows the amplifier to achieve high gain over a more relaxed time period without the abrupt performance degradation that occurs in single-transistor-type amplifiers when entering the triode region.
Solution Approach 2:
The balanced push-pull structure provides inherent feedback mechanisms that stabilize the operating point. The complementary transistor pair automatically compensates for variations in operating conditions, reducing sensitivity to timing precision requirements while maintaining high gain over an extended period.
3Manufacturing precision
If the amplifier operates for a longer duration to achieve desired gain, then the gain increases, but noise becomes dominant and signal-to-noise ratio decreases
Solution Approach 1:
The complementary push-pull configuration provides differential feedback that cancels common-mode noise signals. By using matched NMOS and PMOS transistors with symmetric characteristics, the amplifier rejects noise that appears equally on both inputs, thereby maintaining signal-to-noise ratio even during extended high-gain operation.
Solution Approach 2:
The invention changes the transconductance parameter by combining contributions from both NMOS and PMOS transistors. This results in higher effective transconductance that achieves the desired gain level faster, reducing the operation duration and consequently the accumulated noise, while maintaining signal integrity.
Data Source
AI summary
A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.