Push-Pull Amplifier Bias Circuit for Low Stand-By Current
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Solution Overview
Problem
Conventional biasing techniques for output transistors in amplifiers result in higher than desired stand-by current, especially when the load current is low, due to inadequate modeling of the actual drain-to-source voltage by diode-connected field-effect transistors, leading to inefficiency and excessive dependence on supply voltage.
Innovation Solution
The proposed solution involves embedding replica transistors in an amplifier loop to impose the proper drain-source voltage and ratio of stand-by current, using complementary amplifier circuits for NMOS and PMOS biasing, and incorporating a second diode-connected device to set the offset gate voltage, ensuring the voltage across the replica output transistor matches the actual output transistor during stand-by conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diode-connected FETs are used as ratio replica devices to set gate voltage, then the output transistors remain in active conduction state, but stand-by current becomes higher than desired and excessively dependent on supply voltage
Solution Approach 1:
The patent implements a feedback mechanism where the bias circuit continuously monitors the actual drain-to-source voltage of the output power transistors and adjusts the gate voltage accordingly. This feedback loop ensures that the output transistors remain in the active conduction state while dynamically optimizing the stand-by current to match actual operating conditions, thereby resolving the contradiction between maintaining reliability and reducing energy consumption.
Solution Approach 2:
The patent changes the biasing parameters by using variable resistance elements (such as MOSFETs operating in triode region) instead of fixed diode-connected FETs. By adjusting the resistance values and bias voltages dynamically, the circuit can maintain proper conduction state while adapting the stand-by current level to actual load conditions and supply voltage variations, thus reducing excessive current draw.
2Ease of operation
If diode-connected FETs are used to produce level shifts, then gate voltage is set, but the stand-by current becomes excessively dependent on supply voltage
Solution Approach 1:
The bias circuit incorporates feedback paths that monitor supply voltage variations and automatically adjust the gate voltage level shifts to compensate. This ensures that the gate voltage setting remains effective across different supply voltage conditions, reducing the excessive dependence while maintaining ease of operation.
Solution Approach 2:
The patent transitions from static diode-connected FET level shifters to dynamic biasing circuits that can adapt their operation based on real-time conditions. The bias circuit dynamically adjusts its characteristics to maintain proper gate voltage setting regardless of supply voltage changes, thereby improving adaptability while preserving ease of operation.
3Power
If large width, minimum-channel-length transistors are used in output stage, then power handling capability is improved, but stand-by current increases due to inadequate voltage modeling
Solution Approach 1:
The bias circuit uses feedback to accurately model and compensate for the drain-to-source voltage effects in large power transistors. By continuously monitoring actual voltage conditions and adjusting gate voltages accordingly, the system maintains the high power handling capability of large-width transistors while eliminating the excessive stand-by current caused by inadequate voltage modeling in conventional circuits.
Solution Approach 2:
The patent introduces intermediate bias circuitry that acts as a mediator between the control signals and the large power transistors. This intermediate stage accurately models the voltage effects and provides properly compensated gate voltages, enabling the power transistors to operate efficiently with low stand-by current while maintaining their high power handling capability.
Data Source
AI summary
Techniques for biasing output transistor of a push-pull amplifier output stage are provided. In certain applications the techniques can improve efficiency of the amplifier. In an example, a circuit can include an output stage including first and second output transistors, a first scaled replica transistor corresponding to the first output transistor, and an amplifier circuit in a feedback arrangement for biasing a gate of the first output transistor at a level that, at a specified stand-by current level of the first output transistor, reproduces a voltage difference between the drain and source terminals of the first output transistor across the drain and source terminals of the first replica transistor.