Push-Pull Buffer Clocking for Linear Phase Interpolators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current phase interpolators suffer from non-linear behavior due to the RC effect caused by load resistors in current mode logic buffers, which affects the linearity of the output clock signals used in phase control.
Innovation Solution
The use of push-pull buffers, which employ pairs of n-FET and p-FET transistors, generates output clock signals with a more linear slope, improving the linearity of phase interpolators by eliminating the need for loading capacitors and reducing semiconductor chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current mode logic buffers with load resistors are used to provide input clock signals to the phase interpolator, then the buffers can drive the clock signals, but the RC effect caused by the load resistors creates non-linear behavior in the output clock signals
Solution Approach 1:
The patent changes the operating parameters of the buffer circuit by using transistors in a push-pull configuration rather than current mode logic with resistive loads. This parameter change eliminates the RC effect while maintaining signal driving capability, thereby improving linearity of the output clock signals without sacrificing drive strength.
2Reliability
If loading capacitors are added to compensate for the RC effect and improve linearity, then the linearity of the phase interpolator improves, but the semiconductor chip area and power consumption increase
Solution Approach 1:
The patent extracts and removes the loading capacitors from the circuit by fundamentally changing the buffer architecture to push-pull configuration. This elimination of external compensation components reduces chip area while maintaining improved linearity through the inherent characteristics of the push-pull transistor arrangement.
Solution Approach 2:
The push-pull transistor configuration acts as an intermediary solution that naturally compensates for the RC effect without requiring additional capacitive elements. The transistor pair provides the necessary signal conditioning and linearity improvement intrinsically, eliminating the need for separate compensation components.
3Reliability
If loading capacitors are added to improve linearity, then the phase interpolator performance improves, but power consumption increases
Solution Approach 1:
The patent removes the loading capacitors that would increase power consumption by introducing additional charging and discharging cycles. The push-pull buffer configuration achieves linearity improvement without these energy-intensive capacitive elements, thereby reducing overall power consumption while maintaining reliability.
Data Source
AI summary
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.