Push-Pull Amplifier Calibration for Low Second-Order Distortion
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Solution Overview
Problem
Existing push-pull amplifiers in integrated circuits face challenges in minimizing second-order distortion due to production tolerances, which affect their linearity and performance, especially in direct conversion receivers where even order nonlinearity is critical.
Innovation Solution
An electronic integrated circuit with a detection circuit having a push-pull amplifier with adjustable transistor size ratios, allowing for calibration by determining the optimal size ratio that minimizes second-order distortion, using a test signal to compare output differences and adjust the size ratio of the push-pull amplifiers in the signal path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If push-pull amplifiers are used to reduce even order non-linearity, then second order distortion is minimized in principle, but production tolerances cause mismatch between complementary transistors that prevents achieving identical analog characteristics
Solution Approach 1:
The patent applies preliminary action by performing calibration during the manufacturing process to pre-adjust the transistor size ratio. A detection circuit measures the actual second-order distortion caused by production tolerances, and based on this measurement, the transistor sizes are adjusted beforehand to compensate for the mismatch. This ensures that when the amplifier is deployed, it already has optimized linearity performance without requiring post-manufacturing adjustments.
Solution Approach 2:
The patent implements feedback by using a detection circuit that measures the second-order distortion output of the push-pull amplifier. This measured distortion is fed back to a control circuit that adjusts the transistor size ratio accordingly. The feedback loop continues until the distortion is minimized, ensuring that the amplifier achieves optimal linearity performance despite production tolerances affecting transistor matching.
2Manufacturing precision
If transistor device sizes are adjusted to compensate for production tolerances, then analog characteristics matching is improved, but device complexity increases due to adjustable size ratios
Solution Approach 1:
The patent applies parameter changes by adjusting the physical size parameter of the transistor devices (width or area) to compensate for production tolerances. Instead of changing the circuit topology or adding complex control mechanisms, the solution simply varies the transistor size parameter during calibration. The detection circuit measures distortion, and based on this measurement, the transistor sizes are modified to achieve optimal matching between complementary devices.
Solution Approach 2:
The patent uses copying by creating a detection circuit that replicates the essential functionality of the push-pull amplifier stage. This detection circuit includes complementary transistor devices with adjustable size ratios that mirror the main amplifier's structure. By calibrating the detection circuit first and then copying those size ratio settings to the main amplifier, the patent achieves consistent optimization across multiple amplifier stages without requiring separate complex calibration mechanisms for each one.
3Reliability
If calibration processes are implemented to minimize second order distortion, then linearity requirements are met, but calibration complexity and measurement requirements increase
Solution Approach 1:
The patent applies taking out by extracting the calibration function into a separate, dedicated detection circuit that is independent of the main signal path. This detection circuit specifically measures second-order distortion without processing the full-bandwidth signal, simplifying the measurement task. By separating the calibration function from the main amplifier operation, the patent reduces the complexity of the overall calibration system while maintaining accurate distortion measurement and adjustment capabilities.
Data Source
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AI summary
An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit (15) with at least one push-pull amplifier (20, 21), wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal (V1) of a push-pull amplifier with an applied test signal (LOin) and a second output signal (V2) of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals (V1, V2) is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.