Push-Pull Clock Buffer for Low-Jitter High-Q Distribution
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Solution Overview
Problem
Conventional clock buffer technologies face challenges in distributing high-speed clock signals across multiple channels with low power consumption while minimizing jitter and noise, as they often require large inductors and result in skew between channels, and conventional CMOS buffers introduce Miller capacitance and phase noise, degrading VCO performance and increasing power consumption.
Innovation Solution
A low-power, low-jitter clock distribution system utilizing a push-pull source follower as a first stage of the clock buffer, which has high Q input capacitance and is not subject to the Miller effect, combined with a second push-pull cascode stage for efficient resonance circuit operation, allowing for zero-power transmission lines and minimal power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock buffer technologies are used to distribute high-speed clock signals, then clock signal distribution is achieved, but power consumption increases and jitter is introduced
Solution Approach 1:
The patent changes the electrical parameters of the buffer circuit by using a push-pull source follower configuration with specific transistor sizing and biasing conditions. This creates a high-Q resonant circuit that operates at the clock frequency, reducing power consumption while maintaining signal integrity through resonant energy storage rather than continuous dissipation.
Solution Approach 2:
The patent utilizes electrical resonance analogous to mechanical vibration principles. The push-pull source follower creates a resonant circuit that oscillates at the clock frequency, storing and releasing energy in a manner similar to mechanical resonators. This resonant operation reduces the continuous power dissipation typical of conventional buffers.
2Reliability
If conventional clock buffer technologies are used, then clock signals can be distributed, but jitter and noise increase degrading VCO performance
Solution Approach 1:
The patent converts the inherently noisy switching action of the push-pull configuration into a beneficial resonant effect. By sizing the transistors and biasing the circuit to operate in a resonant mode, the switching noise is transformed into a clean sinusoidal output at the clock frequency, filtering out harmonics and reducing jitter while maintaining the driving capability.
3Use of energy by moving object
If large inductors are used in conventional clock buffers, then power consumption is reduced, but channel skew increases
Solution Approach 1:
The patent extracts and eliminates the large inductor component from the clock buffer circuit. The push-pull source follower configuration achieves resonant operation through the intrinsic capacitance of the transistors and minimal external components, removing the source of channel skew while maintaining low power consumption through the resonant mechanism.
4Reliability
If CMOS buffers are used, then clock signal distribution is achieved, but Miller capacitance increases degrading performance
Solution Approach 1:
The patent inverts the conventional CMOS buffer approach by using a push-pull source follower configuration where the output impedance is transformed through the resonant circuit. This inversion of the impedance transformation approach minimizes the Miller capacitance effect by ensuring that the feedback capacitance does not get multiplied by the voltage gain, as the resonant operation maintains a unity gain buffer configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system enables efficient distribution of high-Q clock signals with reduced power consumption and minimal jitter, maintaining high Q ratios and preventing energy loss, thus improving the accuracy and efficiency of clock signal transmission across multiple channels.
Implementation Method 1
A low-power, low-jitter clock distribution system utilizing a push-pull source follower as a first stage of the clock buffer, which has high Q input capacitance
Data Source
AI summary
An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.