Push-Pull Flash Memory Cell Independent Programming

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Solution Overview

Problem

Existing push-pull non-volatile memory cells face challenges in independent programming and erasure of p-channel and n-channel transistors without disturbing each other, and in simplifying programming circuitry due to shared floating gates.

Innovation Solution

The proposed solution involves a push-pull non-volatile memory cell design with a p-channel flash transistor connected in series with an n-channel flash transistor, an n-channel switch transistor, and an additional n-channel assist transistor, using band-to-band programming and hot carrier injection programming methods, along with shared floating gates to simplify programming and erasure processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a push-pull memory cell uses p-channel and n-channel transistors with shared floating gates, then the device can achieve non-volatile memory functionality, but independent programming and erasure of each transistor becomes difficult without disturbing the other

Engineering Contradiction:

Improveindependent programming capabilityVSAvoidprogramming circuitry complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the programming control into separate pathways by introducing distinct control gates (CG0, CG1) for each transistor type. The p-channel transistor can be programmed independently through CG0 while the n-channel transistor remains unaffected, and vice versa. This segmentation of control mechanisms resolves the interference problem while maintaining non-volatile memory functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces control gates as intermediary elements that mediate between the programming signals and the floating gates. These control gates act as intermediaries that enable selective programming by controlling which transistor's floating gate receives the programming signal, thereby preventing disturbance to the other transistor.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If the memory cell uses shared floating gates for both p-channel and n-channel transistors, then manufacturing is simplified, but programming circuitry complexity increases

Engineering Contradiction:

Improvefloating gate fabricationVSAvoidprogramming circuitry

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

While maintaining shared floating gates for manufacturing simplicity, the patent segments the control mechanism by providing separate control gates for each transistor type. This allows independent programming control without requiring separate floating gates, thus preserving manufacturing ease while reducing programming circuitry complexity through systematic control separation.

Inventive Principle:

Principle #1Segmentation

3Productivity

If conventional programming voltages are applied to flash transistors, then programming can be achieved, but the programming process disturbs the other transistor in the push-pull configuration

Engineering Contradiction:

Improveprogramming speedVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The control gates serve as intermediaries that enable selective activation of programming pathways. When programming the p-channel transistor, the control gate configuration ensures that programming signals are directed only to the p-channel transistor's floating gate, preventing disturbance to the n-channel transistor, thus maintaining data integrity while enabling fast programming.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies local quality by creating different electrical conditions for each transistor during programming. By controlling the potential distribution through separate control gates, the programming signal is localized to the target transistor's floating gate region, preventing unwanted effects on the other transistor while maintaining programming efficiency.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design allows for independent read and programming of n-channel and p-channel transistors without disturbing each other, reducing the complexity of programming circuitry and enhancing the coupling ratios of flash transistors, while using Fowler-Nordheim tunneling for erasure.

Implementation Method 1

using Fowler-Nordheim tunneling for erasure

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

using band-to-band programming and hot carrier injection programming methods

Methodology Applied

Scientific EffectHot carrier injection:

Data Source

PatentUS7839681B2Push-pull FPGA cell

Publication Date: 2010.11.23 MICROSEMI SOC CORP

AI summary

A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.