Push-Pull Common-Gate Power Amplifier for Linearity and PAE

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Solution Overview

Problem

Existing amplifying circuits face a trade-off between power consumption and linearity, with nonlinear circuits having high power amplifier efficiency (PAE) and linear circuits having low PAE, necessitating a balance between the two.

Innovation Solution

A push-pull common gate power amplifying circuit design using NMOS and PMOS transistors, with specific bias voltage configurations and a matching circuit to combine output signals, eliminating even harmonics and achieving linear amplification with high efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If linear amplifying circuits are used, then linearity is improved, but power amplifier efficiency deteriorates

Engineering Contradiction:
ImprovelinearityVSAvoidpower amplifier efficiency
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The amplifying circuit is divided into two separate push-pull amplifying circuits: a first push-pull amplifying circuit that amplifies the input signal to produce a first output signal, and a second push-pull amplifying circuit that amplifies the inverted input signal to produce a second output signal. These two circuits operate in parallel with complementary symmetry, allowing the even harmonics generated by each circuit to cancel each other out when combined, thereby achieving high linearity while maintaining good power amplifier efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The output signals from the first and second push-pull amplifying circuits are combined through a matching circuit. The first output signal and the second output signal are merged in such a way that the even harmonics cancel each other due to the complementary symmetry of the push-pull configuration, while the fundamental frequency components add constructively. This combining approach achieves harmonic cancellation and improves linearity without sacrificing power efficiency

Inventive Principle:
Principle #5Merging (Combining)

2Use of energy by moving object

If nonlinear amplifying circuits are used, then power amplifier efficiency is improved, but linearity deteriorates

Engineering Contradiction:
Improvepower amplifier efficiencyVSAvoidlinearity
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent converts the harmful effect of even harmonics generated by push-pull amplifying circuits into a beneficial outcome. By using complementary symmetry between the first and second push-pull amplifying circuits and combining their outputs through a matching circuit, the even harmonics from each circuit cancel each other out. This transforms what would normally be a source of distortion into a mechanism for achieving high linearity while maintaining the high power amplifier efficiency characteristic of nonlinear circuits

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12489401B2Power amplifying circuits
Publication Date: 2025.12.02 REALTEK SEMICON CORP
  • US12489401B2 patent drawing
  • US12489401B2 patent drawing
  • US12489401B2 patent drawing

AI summary

A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.