Push-Pull Buffer Phase Interpolators With Improved Clock Linearity
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Solution Overview
Problem
Current mode logic buffers introduce non-linear behavior in phase interpolators due to the RC effect, which affects the linearity of output clock signals, requiring reduced edge rates and increased chip area and power consumption.
Innovation Solution
Employing push-pull buffers with n-FET and p-FET transistor pairs to generate output clock signals for phase interpolators, providing a more linear slope and eliminating the need for loading capacitors, thus improving linearity and reducing chip area and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current mode logic buffers are used to provide input clock signals to phase interpolator, then linearity of phase interpolator operation is improved, but RC effect introduces non-linear behavior affecting output signal linearity
Solution Approach 1:
The patent changes the operational parameters of the buffer circuit by using current mode logic with specific transistor configurations (n-FET and p-FET pairs) and biasing schemes. This transforms the buffer's output characteristics to provide constant current drive, eliminating the RC effect that causes non-linear behavior in traditional resistive-loaded buffers.
Solution Approach 2:
The patent replaces the traditional resistive load mechanism with an active current mode logic system using transistor pairs. This substitution eliminates the physical RC time constant effect by using voltage-mode to current-mode conversion, where the output is driven by controlled current sources rather than resistive loads.
2Measurement precision
If current mode logic buffers are used to improve linearity, then phase accuracy is enhanced, but chip area and power consumption increase
Solution Approach 1:
The patent merges the buffer function with the phase interpolator input stage by integrating current mode logic circuits directly at the interpolator input. This consolidation eliminates the need for separate buffering stages and loading capacitors, reducing overall chip area while maintaining the linearity benefits of current mode operation.
Solution Approach 2:
The patent extracts and eliminates the loading capacitors from the circuit design. By using current mode logic buffers that provide inherent constant current drive, the patent removes the need for external capacitive loading elements, thereby reducing chip area and parasitic effects.
3Manufacturing precision
If current mode logic buffers are used to improve linearity, then phase interpolator performance is enhanced, but power consumption increases
Solution Approach 1:
The patent employs dynamic current steering in the phase interpolator where current mode logic buffers dynamically switch between different current paths based on control signals. This dynamic operation allows precise phase control with constant total current draw, optimizing power efficiency while maintaining linearity across the full phase range.
Solution Approach 2:
The patent changes the biasing parameters and operating points of the transistor circuits to optimize the trade-off between linearity and power consumption. By carefully controlling gate voltages and current mirror ratios, the circuit achieves high linearity with minimized power dissipation.
Data Source
AI summary
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.