Push-Pull Output Circuit With Symmetric MOS Transistor Drive
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Solution Overview
Problem
Conventional MOS output circuits exhibit low symmetry in drive circuits for p-channel and n-channel output transistors, leading to varying transfer characteristics depending on the input signal polarity, resulting in asymmetrical transfer characteristics and reduced symmetry in audio amplifier performance.
Innovation Solution
The proposed output circuit employs a gm amplifier and vertically stacked current mirror circuits to equalize gate-source voltages of p-channel and n-channel output transistors, ensuring high symmetry in drive circuits and transfer characteristics, thereby stabilizing idle current and enhancing audio amplifier performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional MOS output circuit uses a simple configuration with MOS transistors and resistances to determine idle current, then the circuit complexity is reduced and chip size is minimized, but the gate impedance of p-channel and n-channel output transistors becomes unequal, resulting in asymmetrical transfer characteristics
Solution Approach 1:
The patent intentionally introduces asymmetry in the bias circuit configuration to compensate for the inherent asymmetry in MOS transistor characteristics. By using different circuit arrangements for p-channel and n-channel transistors, the patent achieves symmetrical transfer characteristics despite the fundamentally different behavior of complementary MOS devices. This involves designing separate bias networks that account for the different threshold voltages and transconductance characteristics of p-channel and n-channel transistors.
2Ease of operation
If equal currents are applied to p-channel and n-channel output transistors, then the drive circuit symmetry is improved, but the transfer characteristic still varies considerably depending on input signal polarity due to unequal gate impedance
Solution Approach 1:
The patent modifies the bias voltage parameters applied to p-channel and n-channel output transistors to compensate for their different gate impedance characteristics. By adjusting the DC bias points and using different resistance values in the bias networks, the patent ensures that both transistors operate at optimal points that yield symmetrical transfer characteristics. This involves carefully selecting bias currents and voltages to balance the overall push-pull operation despite inherent device asymmetries.
Data Source
AI summary
According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.