Push-Push Frequency Doubler With Transformer Isolation From Supply Impedance
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Solution Overview
Problem
Existing frequency multiplier circuits in automotive radar systems suffer from sensitivity to impedance of power supply paths, high complexity, large silicon area, and power consumption, as well as the challenge of controlling supply-path impedance, which affects radar sensitivity and performance.
Innovation Solution
A push-push frequency doubler circuit with AC-isolation from power supply achieved through DC-feed like components and a bypass return path, utilizing a cascode topology to provide high conversion gain and reduce current consumption, while eliminating the need for trimming elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional frequency multiplier circuits are used, then frequency multiplication is achieved, but sensitivity to supply path impedance increases and radar performance deteriorates
Solution Approach 1:
The patent introduces an intermediary impedance transformation network between the frequency multiplier circuit and the power supply path. This network transforms the high impedance presented by the frequency multiplier at the supply path into a lower impedance that is less sensitive to supply variations, thereby mediating the harmful interaction between the multiplier and power supply impedance
Solution Approach 2:
The patent modifies the impedance parameters of the supply path by introducing transformation networks that change the effective impedance seen by the frequency multiplier circuit. This parameter transformation reduces the sensitivity to supply path impedance variations while maintaining the frequency multiplication function
2Reliability
If complex frequency multiplier architectures are used, then frequency multiplication is achieved, but device complexity and silicon area increase
Solution Approach 1:
The patent divides the frequency multiplication function into separate stages: a core frequency multiplier circuit and a separate impedance transformation network. This segmentation allows each part to be optimized independently, reducing overall complexity while maintaining stability
Solution Approach 2:
The patent introduces intermediary impedance transformation networks that act as mediators between the simple core multiplier and the power supply, providing the necessary impedance matching without requiring complex architecture in the core multiplication circuit
3Reliability
If conventional frequency multiplier circuits are used, then frequency multiplication is achieved, but current consumption increases
Solution Approach 1:
The patent introduces intermediary impedance transformation networks that improve power transfer efficiency by matching impedances. This reduces reflected power and minimizes the current required to achieve the desired output power level, thereby reducing overall current consumption while maintaining multiplication accuracy
Data Source
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AI summary
A circuit (12), comprising: frequency multiplier circuitry (120) having input nodes (INp, INN) configured to receive an input signal (Vf0) and an anti-phase version thereof, the input signal (Vf0) having a first frequency value, the frequency multiplier circuitry (120) configured to produce a current signal (i2f0) at a second frequency value that is an even multiple of the first frequency value; a transformer (122) comprising a primary side (Lp, Cp) and a secondary side (Ls, Cs), wherein the primary side (Lp, Cp) of the transformer (122) comprises a primary inductance (Lp) coupled (126) to the frequency multiplier circuitry (120) to receive the current signal (i2f0) therefrom, wherein the secondary side (Ls, Cs) of the transformer (122) is configured to provide a frequency multiplied voltage signal (VOUT); wherein the frequency multiplier circuitry (120) and the transformer (122) are cascaded between at least one first node (D) and a second node (S), the at least one first node (D) and the second node (S) configured to be coupled to a supply node (VDD) and ground (GND); a first shunt resonator (124a) coupled between the supply node (VDD) and the at least one first node (D); a second shunt resonator (124b) coupled between the second node (S) and ground (GND), and a bypass current path (126) coupled between the at least one first node (D) and the second node (S).