Pushbuffer Synchronization for GPU Thread Execution

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Solution Overview

Problem

Existing parallel processing systems lack a mechanism for synchronizing computing thread arrays and launching threads or groups of threads, leading to inefficiencies in GPU utilization and resource management.

Innovation Solution

A pushbuffer system is implemented to synchronize processing work by allowing the CPU to write launch commands and dependencies for thread arrays, enabling the GPU to autonomously execute threads and delay or reorder their execution based on completion status, thereby keeping the GPU busy and efficient.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the GPU waits for the CPU to issue new commands, then the CPU can maintain control over execution order, but the GPU utilization decreases and throughput is reduced

Engineering Contradiction:
ImproveGPU utilizationVSAvoidCPU control over execution order
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The CPU pre-issues multiple launch commands to the pushbuffer in advance, specifying dependencies between thread arrays. The GPU then autonomously executes these commands according to the specified dependencies without requiring continuous CPU intervention, thereby improving GPU utilization while maintaining execution order control.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pushbuffer acts as an intermediary data structure between the CPU and GPU. It stores launch commands and dependency information, allowing the CPU to communicate execution requirements in advance while the GPU autonomously processes them, resolving the contradiction between GPU autonomy and CPU control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the GPU executes threads in strict FIFO order from the pushbuffer, then command ordering is preserved, but the GPU may remain idle waiting for previous commands to complete

Engineering Contradiction:
ImproveGPU throughputVSAvoidCommand execution ordering
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically determines execution order based on dependency relationships rather than strict FIFO ordering. The GPU analyzes the dependency graph of launch commands and executes thread arrays as soon as their dependencies are satisfied, optimizing throughput while preserving logical execution order through the dependency specification mechanism.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the CPU loads all launch commands into the pushbuffer in advance, then the GPU can operate autonomously and remain busy, but the system requires more memory bandwidth and buffer space

Engineering Contradiction:
ImproveGPU autonomous operationVSAvoidmemory bandwidth and buffer space
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The CPU loads a partial set of launch commands into the pushbuffer at a time - enough to keep the GPU busy for a reasonable period without overwhelming memory bandwidth or buffer space. This balanced approach enables autonomous GPU operation while avoiding excessive memory resource consumption.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7526634B1Counter-based delay of dependent thread group execution
Publication Date: 2009.04.28 NVIDIA CORP
  • US7526634B1 patent drawing
  • US7526634B1 patent drawing
  • US7526634B1 patent drawing

AI summary

Systems and methods for synchronizing processing work performed by threads, cooperative thread arrays (CTAs), or “sets” of CTAs. A central processing unit can load launch commands for a first set of CTAs and a second set of CTAs in a pushbuffer, and specify a dependency of the second set upon completion of execution of the first set. A parallel or graphics processor (GPU) can autonomously execute the first set of CTAs and delay execution of the second set of CTAs until the first set of CTAs is complete. In some embodiments the GPU may determine that a third set of CTAs is not dependent upon the first set, and may launch the third set of CTAs while the second set of CTAs is delayed. In this manner, the GPU may execute launch commands out of order with respect to the order of the launch commands in the pushbuffer.