PV Output Optimizer Circuit With Surge-Protected Step-Down Path
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Solution Overview
Problem
Existing solar photovoltaic output optimizer circuits fail to effectively protect switching transistors from surge voltages during low output states, leading to potential transistor breakage and energy wastage.
Innovation Solution
Incorporating a step-down circuit in conjunction with the step-up circuit, which includes a surge protection mechanism using additional switching transistors and diodes to manage energy flow and prevent surge voltages, and utilizing a transformer and voltage doubler rectification to stabilize output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PV optimizer circuit is used, then the circuit can operate during normal power generation, but switching transistors are vulnerable to surge voltages during low output states leading to potential breakage
Solution Approach 1:
The patent applies beforehand cushioning by introducing a surge protection circuit with a third switching transistor, third diode, and inductance that activates before surge voltages can damage the main switching transistors. During low power generation states, when surge voltages occur, the protection circuit provides a safe discharge path for the surge energy through the inductance and diode, preventing direct exposure of the main transistors to harmful voltage spikes.
2Productivity
If the PV panel operates at low light conditions, then power generation continues, but internal impedance increases causing voltage reduction and unstable power source operation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the operating parameters of the PV optimizer circuit based on the power generation state. The control circuit monitors generation levels and switches between different operating modes: during low light conditions, it activates the surge protection circuit and adjusts switching frequencies to maintain stable operation despite high internal impedance, while during normal conditions it operates in standard mode for maximum efficiency.
3Reliability
If additional surge protection components are added to the circuit, then transistor protection is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the surge protection circuit with the existing PV optimizer circuit architecture. The third switching transistor is incorporated into the same circuit board and control system, sharing common elements such as the control circuit, housing, and power management ICs. This consolidation provides comprehensive protection while minimizing the increase in overall device complexity through shared components and unified design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures stable operation and high power generation efficiency by preventing transistor breakage and utilizing generated energy without waste, even at low output states of the solar photovoltaic panel.
Implementation Method 1
a transformer T1 where one end a of a primary winding is connected to a connection point between the source electrode of the second switching transistor Q2 and the drain electrode of the third switching transistor Q3
Implementation Method 2
a first diode D1 whose anode electrode is connected to one end c of the secondary winding of the transformer T1 and whose cathode electrode is connected to a '+' output terminal
Data Source
AI summary
A solar photovoltaic output optimizer circuit utilizes generated energy without waste. The optimizer circuit includes a solar photovoltaic power generation input device for receiving the generated output of a solar photovoltaic panel, a switching device, and a voltage doubler rectification device, and further includes: a first power collection circuit that connects a connection point between a source electrode of a second switching transistor of the switching device and one end of a primary winding of a transformer of the voltage doubler rectification device to a drain electrode of a sixth switching transistor; and a second power collection circuit including a seventh switching transistor whose drain electrode is connected to a drain electrode of a fifth switching transistor of the switching device and whose source electrode is connected to a source electrode of the sixth switching transistor of the first power collection circuit and an anode electrode of a third diode.