PVD Conductive Fill for Semiconductor Interconnections
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Solution Overview
Problem
The semiconductor industry faces challenges in accurately controlling deposition and patterning processes during metallization interconnection fabrication, leading to potential deterioration of electrical performance in semiconductor devices due to inaccuracies and improper control.
Innovation Solution
A physical vapor deposition (PVD) process is employed to form conductive features, such as metal contacts and vias, with multiple stages of temperature and bias power control, eliminating the need for a copper seed layer and reducing voids and seams in high aspect ratio openings, thereby enhancing gap fill performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deposition and patterning processes are used for metallization interconnection fabrication, then the process can be completed with standard procedures, but the electrical performance of the device structures deteriorates due to inaccurate and improper control
Solution Approach 1:
The deposition process is divided into multiple sequential stages: initial deposition stage, intermediate deposition stage, and final deposition stage. Each stage has specific parameter ranges (temperature, bias power, deposition rate) optimized for its purpose, allowing precise control over the conductive feature formation and eliminating the need for copper seed layers while improving electrical performance
Solution Approach 2:
The patent employs dynamic adjustment of deposition parameters during the process. Temperature is varied from room temperature to elevated temperatures (e.g., 50-150°C), bias power is modulated throughout deposition, and deposition rate is controlled at different stages. This dynamic parameter control enables accurate formation of conductive features with minimal voids and seams
2Ease of manufacture
If a copper seed layer is used in conventional processes, then the deposition can proceed with standard methods, but the process complexity increases and gap fill performance deteriorates due to voids and seams
Solution Approach 1:
The patent extracts and eliminates the copper seed layer from the conventional metallization process. By using a modified PVD process with controlled temperature and bias power parameters, the method directly deposits conductive material without requiring the intermediate copper seed layer, thereby simplifying the manufacturing process and improving gap fill performance
Solution Approach 2:
The patent performs preliminary surface preparation and parameter optimization before the main deposition process. The substrate is pre-conditioned with specific temperature and bias power settings that enable direct deposition of high-quality conductive features, eliminating the need for subsequent copper seed layer formation
3Productivity
If standard deposition parameters are used, then the process can be completed quickly, but the gap fill performance deteriorates with voids and seams in high aspect ratio openings
Solution Approach 1:
The deposition process uses periodic variation of bias power and temperature parameters across three distinct stages. The initial stage uses lower bias power for nucleation, the intermediate stage increases bias power for densification, and the final stage optimizes for surface quality. This periodic parameter adjustment ensures complete gap fill without voids or seams while maintaining efficient deposition rates
Solution Approach 2:
The patent systematically changes deposition parameters including temperature (from room temperature to 50-150°C), bias power (varying across deposition stages), and deposition rate throughout the process. These parameter changes are specifically optimized to achieve superior gap fill performance in high aspect ratio openings without sacrificing productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PVD process ensures precise control over the formation of conductive features, improving electrical performance by minimizing voids and seams, and eliminating the need for a copper seed layer, thus providing a more efficient and accurate method for semiconductor interconnection structures.
Implementation Method 1
A physical vapor deposition (PVD) process is employed to form conductive features
Data Source
AI summary
The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.