PVD Target Edge Roughness Control for Arc-Free Deposition

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Solution Overview

Problem

Existing physical vapor deposition (PVD) systems face issues with contamination accumulation and arcing due to target edge roughness, leading to inefficient operations, increased maintenance, and wafer defects.

Innovation Solution

A PVD system design where the target edge is processed to limit the roughness extension to a specific distance, combined with a gas conducting structure for uniform gas flow, reducing contamination and arcing, and enhancing plasma stability and deposition efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the target edge is left with natural roughness, then the manufacturing process is simpler, but contamination accumulates and arcing occurs leading to wafer defects

Engineering Contradiction:
Improvetarget processing simplicityVSAvoidcontamination accumulation and arcing
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The target edge is pre-processed before PVD deposition to create a specific geometric profile with controlled roughness extension. This preliminary action prevents contamination accumulation and arcing during subsequent deposition processes, eliminating the need for complex real-time monitoring and cleaning mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Only the edge portion of the target within a specific distance from the target surface is processed to have controlled roughness, while the rest of the target maintains its natural properties. This localized processing approach minimizes the impact on overall target performance while effectively preventing contamination and arcing issues.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If the target edge roughness is extended further from the target surface, then there is more tolerance in manufacturing, but contamination and arcing increase leading to more wafer defects

Engineering Contradiction:
Improveedge roughness toleranceVSAvoidcontamination and arcing
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent specifies a critical parameter threshold by limiting the roughness extension to at most 6mm from the target surface. This parameter change optimizes the balance between manufacturing tolerance and harmful effects, preventing contamination accumulation and arcing while maintaining adequate manufacturing flexibility.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If no gas conducting structure is used, then the device complexity is reduced, but gas flow uniformity is poor leading to plasma instability

Engineering Contradiction:
Improvegas conducting structureVSAvoidplasma stability
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

A gas conducting structure is introduced as an intermediary component to distribute process gas uniformly across the PVD chamber. This structure mediates between the gas source and the target/wafer system, ensuring stable plasma conditions and consistent deposition rates without requiring complex control systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If the target edge roughness is not controlled, then maintenance requirements are lower initially, but operational efficiency decreases due to contamination and arcing

Engineering Contradiction:
Improveoperational efficiencyVSAvoidmaintenance requirements
Core Design Contradiction:
ProductivityVSEase of repair

Solution Approach 1:

The target edge is pre-processed to an optimized geometric profile before installation, which prevents contamination accumulation and arcing during operation. This preliminary action maintains high operational efficiency throughout the target's service life and reduces the frequency and complexity of maintenance interventions.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution results in reduced contamination and arcing, improved operational efficiency, fewer wafer defects, and decreased maintenance requirements by controlling the target edge roughness and utilizing a gas conducting structure for uniform plasma distribution.

Implementation Method 1

A physical vapor deposition (PVD) system has a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 2

The gas conducting structure provides for an increased uniformity of flow and/or distribution of the first gas into the PVD volume

Methodology Applied
Scientific EffectGas conduction: Conduction (electrical)

Implementation Method 3

The gas conducting structure provides for an increased concentration and/or density of the first gas in an upper region of the PVD volume, as compared to systems that do not have the gas conducting structure. The increased concentration and/or density of the first gas and/or the increased concentration and/or density of the plasma established in the upper region provides for more efficient operation of the PVD system

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS20240376592A1Physical vapor deposition (PVD) system and method of processing target
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240376592A1 patent drawing
  • US20240376592A1 patent drawing
  • US20240376592A1 patent drawing

AI summary

A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.