Programmable Vector Processor Twiddle Factor Generation
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Solution Overview
Problem
Conventional pipelined FFT architectures for wireless communication networks, particularly in LTE transceivers, face challenges with complexity, resource utilization, and scalability when processing various FFT sizes and mixed-radix operations, leading to inefficiencies in hardware resources and configuration difficulties.
Innovation Solution
A programmable vector processor (PVP) with a ping-pong vector memory bank, twiddle factor generator, and configurable mixed radix engine, capable of performing radix3, radix4, radix5, and radix6 DFT calculations, is introduced. This PVP includes a vector memory address generator and dynamic scaling factor calculator, enabling efficient storage and processing of data through a vector pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional pipelined architectures utilize multiple physical radix processors organized in series, then data streaming capability is improved, but device complexity and hardware resource consumption increase
Solution Approach 1:
The patent implements a single reconfigurable radix processor that can dynamically perform different radix operations (radix-2, radix-3, radix-4, radix-5, radix-6) by loading appropriate twiddle factor vectors, replacing the need for multiple dedicated physical processors. This universal processor maintains data streaming capability while significantly reducing hardware resource consumption and device complexity.
Solution Approach 2:
The processor employs dynamic reconfiguration through programmable control logic that can change the radix operation type and twiddle factor vector dimensions during runtime. This dynamic adaptability allows one processor to function as multiple specialized processors would, reducing hardware resources while maintaining productivity.
2Adaptability or versatility
If conventional architectures are configured to support multiple FFT sizes with mixed-radix processing, then adaptability is improved, but device complexity and configuration difficulty increase
Solution Approach 1:
The processor supports multiple FFT sizes and mixed-radix operations by dynamically changing operational parameters through programmable control. The control logic receives configuration data specifying the desired radix operation and loads corresponding twiddle factor vectors with appropriate dimensions and values, enabling flexible adaptation to different FFT sizes without increasing device complexity.
Solution Approach 2:
A single reconfigurable processor unit handles all mixed-radix operations (radix-2, radix-3, radix-4, radix-5, radix-6) and multiple FFT sizes through universal control logic and programmable twiddle factor loading, eliminating the need for multiple dedicated processor configurations and simplifying the overall system architecture.
3Speed
If multiple stages of FFT radix processors are used in pipelined mode, then processing speed is improved, but resource consumption increases
Solution Approach 1:
The single reconfigurable processor operates in periodic cycles, dynamically switching between different radix operations for different data blocks. Each cycle performs one radix operation type, then reconfigures for the next, achieving pipelined processing throughput without requiring multiple physical processor stages, thus maintaining speed while reducing resource consumption.
Solution Approach 2:
The processor dynamically reconfigures its operational parameters and twiddle factor vectors between processing cycles to handle different radix operations sequentially. This dynamic time-multiplexing approach enables multiple processing functions in a single resource, reducing hardware quantity while maintaining processing speed through efficient time-ordered execution.
Data Source
AI summary
Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.