In-Package Voltage Regulator Power Delivery for Multi-Chip Packages
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Solution Overview
Problem
The complexity of manufacturing multi-chip packages leads to issues such as poor structural configuration and delamination, resulting in high yield loss and increased costs, due to the large number of manufacturing steps and small scale of these packages.
Innovation Solution
The implementation of multi-chip package structures that include Integrated Passive Device (IPD) capacitors and in-Package Voltage Regulators (PVR) with on-die inductors to improve power delivery and electrical performance, such as embedding IPD capacitors beneath the substrate for noise decoupling and using PVRs with buck converters to power dies, which reduces losses and enhances performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip packages are manufactured with increased integration and miniaturization, then functionality and circuitry density are improved, but manufacturing complexity increases leading to poor structural configuration and delamination
Solution Approach 1:
The patent divides the multi-chip package into modular units with standardized interconnection interfaces. Each chip module can be independently manufactured and tested before final assembly, reducing the complexity of manufacturing the entire package as a single complex structure.
Solution Approach 2:
The patent implements a hierarchical packaging structure where chips are mounted on substrates, which are then assembled into multi-chip modules, which in turn are integrated into the final package. This nested arrangement allows systematic management of complexity at each level.
2Adaptability or versatility
If the number of manufacturing steps is increased to achieve higher integration, then functionality is improved, but yield loss increases due to delamination and structural issues
Solution Approach 1:
The patent performs preliminary assembly and testing of chip modules on substrates before final package integration. This allows defects to be detected and corrected at intermediate stages, preventing cumulative errors and reducing final yield loss.
Solution Approach 2:
The patent incorporates protective underfill materials and stress-compensation structures between chips and substrates before final assembly. These pre-installed protective elements prevent delamination and structural failures during subsequent manufacturing steps.
3Volume of moving object
If chip size is reduced for miniaturization, then package density is improved, but power delivery capability deteriorates due to increased resistance and inductance
Solution Approach 1:
The patent transitions from planar power distribution to three-dimensional vertical interconnections using through-substrate vias and stacked chip arrangements. This dimensional change reduces current path length and parasitic inductance, improving power delivery despite miniaturization.
Solution Approach 2:
The patent introduces intermediate power distribution substrates and embedded passive components (inductors, capacitors) within the package structure. These intermediary elements facilitate efficient power delivery to small chips by providing localized voltage regulation and reducing trace inductance.
4Ease of manufacture
If traditional power delivery methods are used in miniaturized packages, then manufacturing simplicity is maintained, but electrical performance deteriorates due to signal integrity issues
Solution Approach 1:
The patent combines active chips with passive components (inductors, capacitors, resistors) into integrated modules mounted on common substrates. This merging reduces the number of separate interconnections needed, maintaining manufacturing simplicity while improving signal integrity through shorter trace lengths.
Solution Approach 2:
The patent uses specialized power distribution substrates with embedded passive components as intermediaries between power sources and chips. These intermediary structures provide controlled impedance pathways and localized decoupling, maintaining electrical performance without complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved electrical performance, including a 3.9% higher maximum clock frequency at a core voltage supply of 1.135 V, and reduces losses as the number of chips increases, thereby addressing the manufacturing challenges and enhancing the reliability of multi-chip packages.
Implementation Method 1
embedding IPD capacitors beneath the substrate for noise decoupling
Implementation Method 2
using PVRs with buck converters to power dies, which reduces losses
Data Source
AI summary
A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.