Complementary Signal Path Duty Cycle Correction Under PVT Variation

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Solution Overview

Problem

In memory applications, duty cycle distortions in clock signals due to process-voltage-temperature variations lead to errors in data retrieval, as the controller may fail to properly align data pulses with clock signals, resulting in missed samples or incorrect recognition of clock edges.

Innovation Solution

A duty cycle correction circuit that includes a complementary signal path with an amplifier circuit and a control circuit to measure duty cycle mismatches, injecting a control current to adjust the gain and common mode voltage of the amplifier circuit, thereby correcting the duty cycle of output signals to align data pulses accurately with clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If duty cycle correction is not applied, then the circuit operation is simple, but data sampling accuracy deteriorates due to duty cycle distortion

Engineering Contradiction:
Improvedata sampling accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the duty cycle of the output signal is measured and compared against a target duty cycle. Based on the measured distortion, a control signal is generated that feeds back to adjust the amplifier circuit, thereby correcting the duty cycle and improving data sampling accuracy without requiring complete circuit redesign

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters of the amplifier circuit dynamically. By adjusting the gain and common mode voltage based on measured duty cycle distortion, the system adapts to maintain accurate timing alignment between clock signals and data pulses, resolving the contradiction between simple operation and sampling accuracy

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If duty cycle distortion occurs due to PVT variations, then the circuit adapts to different conditions, but data retrieval reliability deteriorates

Engineering Contradiction:
ImprovePVT variation adaptationVSAvoiddata retrieval reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The feedback loop continuously monitors duty cycle distortion caused by PVT variations and generates corrective control signals. This allows the system to maintain reliable data retrieval despite adapting to different process, voltage, and temperature conditions, as the measured distortion is actively compensated

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-correction by measuring its own duty cycle distortion and automatically adjusting its parameters. This self-service mechanism ensures that the circuit maintains data retrieval reliability while adapting to PVT variations without external intervention

Inventive Principle:
Principle #25Self-service

3Object-affected harmful factors

If controller RC components filter clock edges, then noise is reduced, but clock edge recognition accuracy deteriorates

Engineering Contradiction:
Improvenoise reductionVSAvoidclock edge recognition accuracy
Core Design Contradiction:
Object-affected harmful factorsVSMeasurement precision

Solution Approach 1:

The patent applies preliminary duty cycle correction to the clock signal before it passes through the controller's RC filtering components. By pre-correcting the duty cycle distortion and aligning clock edges accurately with data pulses, the system ensures that even after RC filtering, the clock edges remain recognizable and properly synchronized for accurate data sampling

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The duty cycle correction circuit effectively aligns data pulses with clock signals, reducing errors in data retrieval by maintaining a stable 50% duty cycle, ensuring accurate sampling and minimizing the impact of duty cycle distortions.

Implementation Method 1

The amplifier circuit is configured to receive a pair of complementary input signals and generate at least one pair of complementary intermediate signals

Methodology Applied
Scientific EffectVoltage amplification:

Implementation Method 2

The control circuit is configured to: measure a duty cycle mismatch between the pair of complementary output signals

Methodology Applied
Scientific EffectDuty cycle measurement:

Implementation Method 3

set at least one of a gain of the amplifier circuit or a common mode voltage of the at least one pair of complementary intermediate signals based on the measured duty cycle mismatch

Methodology Applied
Scientific EffectGain adjustment:

Implementation Method 4

set at least one of a gain of the amplifier circuit or a common mode voltage of the at least one pair of complementary intermediate signals

Methodology Applied
Scientific EffectCommon mode voltage control:

Data Source

PatentUS10284182B2Duty cycle correction scheme for complementary signals
Publication Date: 2019.05.07 SANDISK TECHNOLOGIES LLC
  • US10284182B2 patent drawing
  • US10284182B2 patent drawing
  • US10284182B2 patent drawing

AI summary

A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.