PVT-Compensated Relaxation Oscillator With Lower Quiescent Current
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Solution Overview
Problem
Existing relaxation oscillators suffer from increased quiescent current and temperature-dependent frequency variations due to their design, which affects power consumption and stability across process, voltage, and temperature (PVT) changes.
Innovation Solution
Incorporating a transistor in series with the capacitor and a comparator circuit input coupled to the transistor, rather than the capacitor, to reduce the time the input voltage spends near the trip voltage, combined with a second transistor to bias the gate voltage of the first transistor, compensating for PVT variations and reducing switching current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a transistor is added in series with the capacitor and comparator input is coupled to the transistor, then quiescent current is reduced, but device complexity increases
Solution Approach 1:
A transistor is introduced as an intermediary component between the capacitor and the comparator input. The transistor's gate is controlled by a bias voltage that keeps it in a high-impedance state during most of the oscillation cycle, effectively blocking current flow to the comparator input. This intermediary structure reduces the quiescent current drawn by the comparator while still allowing the necessary signal transmission when needed.
2Device complexity
If the comparator input is coupled directly to the capacitor, then the circuit is simpler, but the input voltage spends too much time near the trip voltage causing increased power consumption
Solution Approach 1:
The transistor serves as a mediator that isolates the comparator input from direct connection to the capacitor. By controlling the transistor's gate with an appropriate bias voltage, the transistor remains in cutoff or high-impedance mode during most of the charging cycle, preventing the comparator input from lingering near the trip voltage threshold and thereby reducing unnecessary switching activity and power consumption.
Solution Approach 2:
The bias voltage applied to the transistor gate is carefully selected to change the transistor's operating state. By adjusting this parameter, the transistor transitions between high-impedance and conductive states, optimizing the timing of when the comparator input receives the capacitor voltage signal. This parameter control ensures the input voltage does not spend excessive time near the trip voltage, reducing power consumption.
3Device complexity
If transistors are used without PVT compensation, then the circuit is simpler, but frequency varies with temperature and process changes
Solution Approach 1:
A feedback mechanism is implemented where a second transistor's gate is coupled to the first transistor's gate, creating a self-biasing arrangement. This feedback structure automatically adjusts the bias conditions in response to PVT variations, compensating for changes in transistor threshold voltages and maintaining stable oscillation frequency across different operating conditions without requiring complex external compensation circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the quiescent current and stabilizes the relaxation oscillator frequency across PVT variations, enhancing power efficiency and performance consistency.
Implementation Method 1
a first transistor coupled to the capacitor and configured to turn off in response to a voltage across the capacitor exceeding a threshold voltage less than a gate voltage of the first transistor
Implementation Method 2
a comparator circuit having an input coupled to the first transistor and an output coupled to a clock node. The comparator circuit is configured to assert its output when a voltage at the input is above a trip voltage
Implementation Method 3
a second transistor configured to increase the gate voltage of the first transistor in response to an increase in a threshold voltage of the second transistor
Implementation Method 4
a current source configured to charge the capacitor
Data Source
AI summary
A device includes a capacitor having a first terminal coupled to a ground node, and a second terminal; a first transistor having a source coupled to the capacitor, a drain coupled to a first node, and a gate; a first current source coupled to the first node and configured to couple to a regulated supply node; a second transistor having a source coupled to the ground node, a drain coupled to a second node, and a gate coupled to the second node and to the gate of the first transistor; and a comparator circuit having an input coupled to the first node and an output configured to couple to a clock node.