PVT-Independent PLL Oscillator for Fast Lock and Low Jitter
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Solution Overview
Problem
Conventional phase locked loops (PLLs) face challenges in achieving fast lock times and low deterministic jitter, particularly at varying temperature, voltage, and process conditions, while also consuming high power and area, and are limited in their ability to operate across multiple center frequencies.
Innovation Solution
A high-performance PLL design featuring a current-controlled oscillator (CCO) based on a scaled replica of a highly stable ring oscillator, which includes a phase frequency detector, charge pump, loop filter, and frequency calibration block, allowing for PVT-independent operation and low jitter performance through a training mode that generates a frequency code for stable frequency generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL architectures are used to improve performance, then lock time and deterministic jitter are reduced, but lock time remains greater than 100 μs and deterministic jitter remains greater than 0.15 UI
Solution Approach 1:
The patent changes the fundamental parameter of the oscillator by using a PVT-independent stable oscillator instead of conventional VCOs. This oscillator maintains stable frequency output despite variations in process, voltage, and temperature, enabling the PLL to achieve lock times less than 100 μs and deterministic jitter less than 0.15 UI across wide operating ranges.
Solution Approach 2:
The patent implements a training mode that performs preliminary frequency calibration and code generation before normal PLL operation. This preliminary action pre-configures the frequency codes and calibrates the oscillator, allowing the PLL to achieve fast lock times when transitioning from idle or power-off states without going through lengthy calibration sequences during normal operation.
2Adaptability or versatility
If LC VCO is used to achieve wide frequency range coverage, then frequency range is extended, but power consumption and area increase
Solution Approach 1:
The patent uses a scaled replica of a highly stable ring oscillator to create the PVT-independent stable oscillator. By copying the successful design of a stable low-frequency oscillator and scaling it to higher frequencies, the patent achieves wide frequency range coverage (1.35 GHz to 2.7 GHz) while maintaining low power consumption and small area, avoiding the need for power-hungry LC VCOs.
3Adaptability or versatility
If conventional VCO with high gain is used to achieve wide frequency range, then frequency range is extended, but deterministic jitter increases
Solution Approach 1:
The PVT-independent stable oscillator is self-regulating and does not require high gain to compensate for variations. The oscillator inherently maintains stable frequency output across PVT variations, eliminating the need for high gain amplification that would otherwise be required to maintain frequency stability. This self-service capability reduces deterministic jitter while maintaining wide frequency range coverage.
4Device complexity
If conventional PLL is used for single centre frequency operation, then circuit is simple, but adaptability to multiple centre frequencies is limited
Solution Approach 1:
The patent implements a universal PLL architecture based on a PVT-independent stable oscillator that can operate at multiple center frequencies (1.35 GHz, 1.8 GHz, and 2.7 GHz). The oscillator's inherent stability across PVT variations allows it to maintain performance at different frequencies without requiring separate calibration procedures or additional compensation circuits, achieving multi-functionality while keeping the circuit relatively simple.
Data Source
AI summary
A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.