Printed Wiring Board Mixed Seed Layer Void Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing printed wiring boards face issues with voids in conductor layers and via conductors, leading to high resistance and potential peeling, which affects the reliability and durability of the board.
Innovation Solution
A printed wiring board design that alternates between conductor layers formed using electroless plating and sputtering, with specific seed layers and electrolytic plating layers, and includes a heat treatment process to minimize voids and enhance adhesion between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electroless plating is used for all conductor layers, then manufacturing process is simple, but voids occur in connecting portions leading to high resistance and peeling
Solution Approach 1:
The patent applies different seed layer formation methods to different locations: electroless plating for conductor layers and sputtering for via conductors. This local differentiation resolves the contradiction by using the appropriate method for each specific application, preventing voids in via conductors while maintaining ease of manufacture for conductor layers.
Solution Approach 2:
The patent changes the formation method parameter from electroless plating to sputtering for via conductors. This parameter change eliminates the void formation issue in via conductors while maintaining the overall manufacturing simplicity, thereby improving connection reliability without significantly complicating the manufacturing process.
2Reliability
If sputtering is used for all conductor layers, then voids are minimized, but manufacturing cost and complexity increase
Solution Approach 1:
The patent applies sputtering only where needed (via conductors) rather than universally. This localized application minimizes voids in critical areas while avoiding the unnecessary complexity and cost of applying sputtering to all conductor layers, thus resolving the contradiction between reliability and manufacturing complexity.
Solution Approach 2:
The patent segments the conductor layer formation process into two distinct methods: electroless plating for conductor layers and sputtering for via conductors. This segmentation allows each method to be applied optimally for its specific purpose, reducing overall complexity compared to universal sputtering while maintaining high reliability.
3Ease of manufacture
If electroless plating is used for via conductors, then manufacturing is easier, but voids form in connecting portions causing high resistance
Solution Approach 1:
The patent changes the formation method parameter from electroless plating to sputtering for via conductors. This parameter change eliminates void formation in connecting portions, achieving higher manufacturing precision in critical areas while the overall process remains relatively simple, thus resolving the contradiction between ease of manufacture and manufacturing precision.
4Quantity of substance
If conventional plating methods are used, then production cost is low, but peeling occurs under stress reducing durability
Solution Approach 1:
The patent applies sputtering locally to via conductors and their connecting portions, while using electroless plating for conductor layers. This localized application provides the enhanced adhesion and void-free structure needed for durability in stress-prone areas without significantly increasing overall production cost, thus resolving the contradiction between cost and durability.
Solution Approach 2:
The patent uses sputtering as an intermediary method for via conductors and connecting portions, which act as mediator layers between different conductor layers and the substrate. This intermediary approach improves adhesion and eliminates voids in critical interfaces, enhancing durability without requiring complete process redesign, thereby maintaining cost-effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces voids in conductor layers and via conductors, improving connection reliability and stability under stress, while maintaining productivity and controlling production costs.
Implementation Method 1
a first conductor layer formed on the first resin insulating layer and including a first seed layer and a first electrolytic plating layer formed on the first seed layer
Implementation Method 2
a second conductor layer formed on the second resin insulating layer and including a second seed layer and a second electrolytic plating layer formed on the second seed layer
Implementation Method 3
a first electrolytic plating layer formed on the first seed layer
Implementation Method 4
a second electrolytic plating layer formed on the second seed layer
Data Source
AI summary
A printed wiring board includes a conductor layer including a pad, a first resin insulating layer laminated on the conductor layer, a first conductor layer formed on the first resin insulating layer and including a first seed layer and a first electrolytic plating layer, a second resin insulating layer laminated on the first insulating layer such that the second resin insulating layer is covering the first conductor layer, and a second conductor layer formed on the second resin insulating layer and including a second seed layer and a second electrolytic plating layer. The first conductor layer is formed such that the first seed layer is an electroless plating layer and the first electrolytic plating layer formed on the first seed layer, and the second conductor layer is formed such that a second seed layer is a sputtering layer and the second electrolytic plating layer formed on the second seed layer.