PWF Metal Gate Cap Modulates Threshold Voltage
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Solution Overview
Problem
Existing techniques for fabricating gate-all-around (GAA) transistors face challenges in scaling down semiconductor IC dimensions, particularly in optimizing the threshold voltage of P-type transistors used in SRAM devices, leading to degraded read margin and Vccmin, and the metal gap-fill issue in semiconductor manufacturing.
Innovation Solution
The use of a P-type work function (PWF) metal gate cap with a tri-layer stack of nitrogen-containing layers (TiN) and optional plasma treatment to modulate the threshold voltage, combined with ALD processing for high-quality metal gate layers to address the gap-fill issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication techniques are used for GAA transistors, then manufacturing process simplicity is maintained, but threshold voltage optimization for P-type transistors is insufficient leading to degraded read margin and Vccmin
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a first metal gate layer for basic gate function, a second metal gate layer with different work function for threshold voltage adjustment, and an interfacial layer for quality enhancement. This segmentation allows independent optimization of each layer's properties to achieve the desired threshold voltage while maintaining manufacturing feasibility.
Solution Approach 2:
Different metal gate layers are applied to different device regions (N-type and P-type transistors) with tailored work functions. The second metal gate layer is selectively formed over specific regions to provide local threshold voltage optimization, enabling improved read margin and Vccmin for P-type transistors without affecting other device characteristics.
2Productivity
If scaling down of semiconductor IC dimensions is continued, then production efficiency and cost reduction are achieved, but manufacturing process complexity increases and existing fabrication techniques become insufficient
Solution Approach 1:
An interfacial layer is formed preliminarily between the metal gate layers and the semiconductor channel to ensure high-quality interfaces before subsequent processing steps. This preliminary action prevents interface defects that would become more critical at scaled dimensions, enabling continued scaling without proportionally increasing process complexity.
Solution Approach 2:
The gate structure employs composite materials consisting of multiple metal layers with different work functions (e.g., tungsten and tantalum nitride) combined with dielectric materials. This composite approach enables precise threshold voltage control and maintains electrical performance at scaled dimensions while using conventional deposition and etching processes.
3Manufacturing precision
If metal gate layers are deposited to achieve proper gap-fill, then complete coverage is achieved, but deposition process complexity and optimization requirements increase
Solution Approach 1:
An interfacial layer acts as an intermediary between the metal gate layers and the semiconductor channel, providing a compliant foundation that facilitates complete gap-fill during deposition. This intermediary layer reduces surface tension and improves wetting, enabling conformal coverage in high-aspect-ratio structures without requiring complex deposition parameter optimization.
Solution Approach 2:
The deposition process is enhanced by considering three-dimensional conformal coverage rather than simple planar filling. Multiple deposition cycles with intermediate annealing steps are used to achieve complete gap-fill in the vertical dimension while maintaining horizontal uniformity, transforming a two-dimensional filling problem into a controlled three-dimensional deposition process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides tunable threshold voltage for P-type transistors, enhancing SRAM read margin and Vccmin while effectively mitigating the metal gap-fill issue, resulting in improved device performance and reliability.
Implementation Method 1
The use of a P-type work function (PWF) metal gate cap with a tri-layer stack of nitrogen-containing layers (TiN) to modulate the threshold voltage
Implementation Method 2
combined with ALD processing for high-quality metal gate layers to address the gap-fill issue
Implementation Method 3
optional plasma treatment to modulate the threshold voltage
Data Source
AI summary
A method and structure for modulating a threshold voltage of a device. In various embodiments, a fin extending from a substrate is provided. In some embodiments, the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some examples, a gate dielectric is formed wrapping around each of the plurality of semiconductor channel layers of the P-type transistor. In some cases, a P-type work function (PWF) metal gate cap is formed wrapping around the gate dielectric. In various embodiments, the PWF metal gate cap merges between adjacent semiconductor channel layers of the plurality of channel layers. Additionally, in some examples, the PWF metal gate cap includes a plurality of nitrogen-containing layers.