PWM Amplifier Ramp Synchronization for Constant Audio Gain
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Solution Overview
Problem
Existing PWM amplifiers require separate ramp generators to maintain constant audio signal gain, leading to phase and frequency offsets that necessitate additional circuitry, such as master and slave PLLs, increasing space consumption in integrated circuits.
Innovation Solution
A PWM amplifier design that incorporates a digital-to-analog converter, synchronization logic circuit, and a single ramp generator capable of switching between high and low voltage supplies, using slope and reference switch signals to generate ramp signals with varying slopes, eliminating the need for separate ramp generators and reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate ramp generators are used to maintain constant audio signal gain when switching between high and low voltage supplies, then the audio signal gain remains constant, but phase and frequency offsets occur requiring additional master and slave PLL circuitry which increases circuit space
Solution Approach 1:
The patent merges the functions of multiple ramp generators into a single ramp generator that serves both high voltage and low voltage supply modes. This single ramp generator produces a single ramp signal that is used by both Y-bridge drivers, eliminating the need for separate ramp generators and their associated PLL synchronization circuitry, thereby reducing circuit space while maintaining constant audio signal gain
Solution Approach 2:
The single ramp generator is designed to perform multiple functions: it generates ramp signals for both high voltage and low voltage supply modes, and its output is used by both Y-bridge drivers. The ramp generator universally provides the timing reference and gain control for the entire PWM amplifier system regardless of which voltage supply mode is active
2Device complexity
If a single ramp generator is used to reduce circuit space, then circuit complexity is reduced, but phase and frequency offsets between multiple Y-bridge drivers may occur
Solution Approach 1:
By merging the ramp generation function into a single source, the patent eliminates the synchronization problem entirely. Both Y-bridge drivers receive their timing reference from the same ramp signal, ensuring perfect phase and frequency alignment without requiring additional PLL circuitry or complex synchronization mechanisms
3Use of energy by moving object
If the Y-bridge driver switches between high and low voltage supplies for optimal power delivery, then power efficiency is improved, but additional circuit control logic is required to manage the switching
Solution Approach 1:
The single ramp generator is designed to universally support both high voltage and low voltage supply modes through its ability to generate appropriate ramp signals for each mode. The circuit control logic leverages the ramp generator's multi-functionality to manage switching between voltage supplies without requiring complex additional synchronization circuitry
Data Source
AI summary
A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.