PWM to Analog Converter Using Fixed-Width Window Counter
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Solution Overview
Problem
Existing methods for converting PWM signals to analog output signals are complex, particularly in designing division operations in silicon and implementing phase locked loops, and existing RC networks are not universal solutions, as they require specific PWM frequency tailoring, making them dependent on input and internal clock frequencies.
Innovation Solution
A circuit comprising a clock signal generator, window generation circuit, counter drive circuit, counter circuit, reset circuit, and digital to analog converter, where a fixed-width calculation window signal is used to count pulses only during the PWM duty cycle, independent of internal and PWM frequencies, allowing for a digital decoder without division operations and achieving accurate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a division operation is implemented to decode the PWM signal, then the duty cycle can be accurately determined, but the circuit complexity increases significantly
Solution Approach 1:
The patent replaces the mathematical division operation (computational approach) with a counter circuit that counts clock pulses during the PWM high period (physical counting approach). This substitution eliminates the need for complex division logic in silicon while maintaining accurate duty cycle measurement through direct pulse counting.
Solution Approach 2:
The patent introduces a clock signal as an intermediary element that enables the conversion of time-based PWM information into a countable digital value. By counting clock pulses that occur during the PWM high period, the system mediates between the analog-like PWM signal and the digital output without requiring division operations.
2Reliability
If a phase locked loop (PLL) is used to convert PWM signals, then frequency synchronization is achieved, but the implementation complexity increases
Solution Approach 1:
The patent extracts only the essential function needed from a full PLL system - the frequency synchronization and pulse counting capability - and implements it through a simplified counter circuit driven by a clock signal. This removes the unnecessary complexity of complete PLL implementation while retaining the beneficial frequency synchronization effect.
3Device complexity
If an RC network is used for PWM conversion, then the circuit simplicity is maintained, but the solution becomes frequency-specific and non-universal
Solution Approach 1:
The patent creates a universal PWM-to-digital conversion circuit that can accurately measure duty cycles at any PWM frequency by using a counter circuit with a clock signal. Unlike RC networks that require frequency-specific component values, this counter-based approach works across a wide frequency range, making it adaptable and versatile while maintaining relative circuit simplicity.
Data Source
AI summary
A circuit for converting a duty cycle of a pulse width modulated signal to an analog value comprising a clock signal generator for generating a clock signal, a window generation circuit for generating a window signal synchronized with the pulse width modulated signal having a window having a window start and a window termination, a counter drive circuit receiving the clock signal, the pulse width modulated signal and the window signal and producing a counter input signal, a counter circuit for counting pulses of the counter input signal and providing a counter output, a reset circuit for resetting the counter at the termination of the window; and a digital to analog converter for converting the counter output at the termination of the window to the analog value.