PWM Data Recovery Circuit With Bit Lock Clock Alignment
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Solution Overview
Problem
Existing PWM data transmission methods between application processors and modulators-demodulators lack synchronization with a reference clock, leading to misalignment and incorrect symbol data generation, which affects data recovery and operation mode changes.
Innovation Solution
A PWM data recovery device incorporating a differential-to-single circuit and alignment buffer that generates PWM bits from differential data signals and activates a bit lock signal to synchronize symbol data transmission with a reference clock, using a phase locked loop reference clock for accurate data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If PWM data transmission is performed without clock synchronization, then data transmission simplicity is improved, but data alignment accuracy deteriorates
Solution Approach 1:
An alignment buffer is introduced as an intermediary component between the PWM data receiver and the data processing unit. The alignment buffer stores received PWM bits and releases them in synchronization with the reference clock, mediating between the asynchronous PWM input and the synchronous processing requirement, thereby resolving the conflict between simple PWM transmission and accurate data alignment
Solution Approach 2:
A bit lock signal mechanism is implemented that detects synchronization patterns in the received PWM data and generates feedback control signals. This feedback system adjusts the data recovery process to maintain proper synchronization with the reference clock, ensuring accurate data alignment while preserving the simplicity of PWM transmission
2Device complexity
If PWM data is recovered without bit lock signal synchronization, then device complexity is reduced, but symbol data recovery accuracy deteriorates
Solution Approach 1:
The system performs preliminary synchronization detection by searching for a known sync pattern in the incoming PWM data stream before正式 data recovery begins. This preliminary action establishes the correct timing reference and activates the bit lock signal, ensuring that subsequent symbol data recovery is performed with accurate synchronization without requiring complex continuous tracking mechanisms
Data Source
AI summary
A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.